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48 LFCSP
Integrated Circuits (ICs)

AD9254BCPZRL7-150

Active
Analog Devices

14-BIT, 150 MSPS, 1.8 V ANALOG-TO-DIGITAL CONVERTER

48 LFCSP
Integrated Circuits (ICs)

AD9254BCPZRL7-150

Active
Analog Devices

14-BIT, 150 MSPS, 1.8 V ANALOG-TO-DIGITAL CONVERTER

Technical Specifications

Parameters and characteristics for this part

SpecificationAD9254BCPZRL7-150
ArchitecturePipelined
ConfigurationS/H-ADC
Data InterfaceParallel
Input TypeDifferential
Mounting TypeSurface Mount
Number of A/D Converters1
Number of Bits14
Number of Inputs1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case48-VFQFN Exposed Pad, CSP
Ratio - S/H:ADC1:1
Reference TypeInternal
Sampling Rate (Per Second)150 M
Supplier Device Package48-LFCSP-VQ (7x7)
Voltage - Supply, Analog [Max]1.9 V
Voltage - Supply, Analog [Min]1.7 V
Voltage - Supply, Digital [Max]3.6 V
Voltage - Supply, Digital [Min]1.7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTape & Reel (TR) 750$ 99.13

Description

General part information

AD9254 Series

The AD9254 is a monolithic, single 1.8 V supply, 14-bit, 150 MSPS analog-to-digital converter (ADC), featuring a high performance sample-and-hold amplifier (SHA) and on-chip voltage reference. The product uses a multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 150 MSPS data rates and guarantees no missing codes over the full operating temperature range.The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and offsets, including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9254 is suitable for applications in communications, imaging, and medical ultrasound.A differential clock input controls all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, Gray code, or twos complement formats. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic.The AD9254 is available in a 48-lead LFCSP_VQ and is specified over the industrial temperature range (−40°C to +85°C).ul.noindent { margin-top:0px; margin-right:0px; margin-bottom:0px; margin-left:15px; padding-top:0px; padding-right:0px; padding-bottom:10px; padding-left:0px;} li.noindent { padding-top:0px; padding-right:0px; padding-bottom:5px; padding-left:0px; margin-top:0px; margin-right:0px; margin-bottom:0px; margin-left:0px;} ol class="noindent"> { margin-top:0px; margin-right:0px; margin-bottom:0px; margin-left:25px; padding-top:0px; padding-right:0px; padding-bottom:10px; padding-left:0px;} li class="noindent">{ padding-top:0px; padding-right:0px; padding-bottom:5px; padding-left:0px; margin-top:0px; margin-right:0px; margin-bottom:0px; margin-left:0px;}Product HighlightsThe AD9254 operates from a single 1.8 V power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.The patented SHA input maintains excellent performance for input frequencies up to 225 MHz.The clock DCS maintains overall ADC performance over a wide range of clock pulse widths.A standard serial port interface supports various product features and functions, such as data formatting (offset binary, twos complement, or Gray coding), enabling the clock DCS, power-down, and voltage reference mode.The AD9254 is pin-compatible with the AD9233, allowing a simple migration from 12 bits to 14 bits.APPLICATIONSUltrasound equipmentIF sampling in communications receiversCDMA2000, WCDMA, TD-SCDMA, and WiMaxBattery-powered instrumentsHand-held scopemetersLow cost digital oscilloscopesMacro, micro, and pico cell infrastructure