ZL30111QDG1
ActiveCLOCK GENERATOR 0.008MHZ TO 19.44MHZ-IN 8.192MHZ-OUT 64-PIN TQFP TRAY
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ZL30111QDG1
ActiveCLOCK GENERATOR 0.008MHZ TO 19.44MHZ-IN 8.192MHZ-OUT 64-PIN TQFP TRAY
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Technical Specifications
Parameters and characteristics for this part
| Specification | ZL30111QDG1 |
|---|---|
| Differential - Input:Output | False |
| Frequency - Max [Max] | 8.192 MHz |
| Input | Clock |
| Main Purpose | POTS Line Card |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | Clock |
| Package / Case | 64-TQFP |
| PLL | True |
| Ratio - Input:Output | 1:5 |
| Supplier Device Package | 64-TQFP (10x10) |
| Voltage - Supply [Max] | 3.5 V |
| Voltage - Supply [Min] | 3.1 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 160 | $ 11.03 | |
| Microchip Direct | TRAY | 1 | $ 13.70 | |
| 25 | $ 11.41 | |||
| 100 | $ 10.38 | |||
| 1000 | $ 9.58 | |||
| 5000 | $ 9.10 | |||
Description
General part information
ZL30111 Series
The ZL30111 POTS line card PLL contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SLIC/CODEC devices.
The ZL30111 generates TDM clock and framing signals that are phase locked to the input reference. It helps ensure system reliability by monitoring its reference for stability and by maintaining stable output clocks during short periods when the reference is unavailable.
Documents
Technical documentation and resources