Integrated Circuits (ICs)

CD74HCT132E

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4-CH, 2-INPUT, 4.5-V TO 5.5-V NAND GATES WITH SCHMITT-TRIGGER INPUTS

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Search across all available documentation for this part.

DocumentsCD54HCT132, CD74HCT132 High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger datasheet CMOS Power Consumption and CPD Calculation (Rev. B)+10

Integrated Circuits (ICs)

CD74HCT132E

Active

Texas Instruments

4-CH, 2-INPUT, 4.5-V TO 5.5-V NAND GATES WITH SCHMITT-TRIGGER INPUTS

Deep-Dive with AI

DocumentsCD54HCT132, CD74HCT132 High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger datasheet CMOS Power Consumption and CPD Calculation (Rev. B)+10

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	CD74HCT132E

Current - Output High, Low [custom]	4 mA
Current - Output High, Low [custom]	4 mA
Features	Schmitt Trigger
Input Logic Level - High [Max]	2.1 V
Input Logic Level - High [Min]	1.9 V
Input Logic Level - Low [Max]	0.6 V
Input Logic Level - Low [Min]	0.5 V
Logic Type	NAND Gate
Max Propagation Delay @ V, Max CL	33 ns
Mounting Type	Through Hole
Number of Circuits	4
Number of Inputs	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Package / Case	14-DIP
Package / Case [x]	0.3 "
Package / Case [y]	7.62 mm
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

CD74HCT132 Series

4-ch, 2-input, 4.5-V to 5.5-V NAND gates with Schmitt-Trigger inputs

Part	Number of Circuits	Mounting Type	Package / Case [x]	Package / Case [y]	Package / Case	Operating Temperature [Min]	Operating Temperature [Max]	Voltage - Supply [Min]	Voltage - Supply [Max]	Input Logic Level - High [Min]	Input Logic Level - High [Max]	Max Propagation Delay @ V, Max CL	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Number of Inputs	Features	Input Logic Level - Low [Min]	Input Logic Level - Low [Max]	Logic Type
Texas Instruments CD74HCT132ME4	4	Surface Mount	0.154 in	3.9 mm	14-SOIC	-55 °C	125 °C	4.5 V	5.5 V	1.9 V	2.1 V	33 ns	4 mA	4 mA	2	Schmitt Trigger	0.5 V	0.6 V	NAND Gate
Texas Instruments CD74HCT132M	4	Surface Mount	0.154 in	3.9 mm	14-SOIC	-55 °C	125 °C	4.5 V	5.5 V	1.9 V	2.1 V	33 ns	4 mA	4 mA	2	Schmitt Trigger	0.5 V	0.6 V	NAND Gate
Texas Instruments CD74HCT132EG4	4	Through Hole	0.3 "	7.62 mm	14-DIP	-55 °C	125 °C	4.5 V	5.5 V	1.9 V	2.1 V	33 ns	4 mA	4 mA	2	Schmitt Trigger	0.5 V	0.6 V	NAND Gate
Texas Instruments CD74HCT132M96	4	Surface Mount	0.154 in	3.9 mm	14-SOIC	-55 °C	125 °C	4.5 V	5.5 V	1.9 V	2.1 V	33 ns	4 mA	4 mA	2	Schmitt Trigger	0.5 V	0.6 V	NAND Gate
Texas Instruments CD74HCT132MTE4	4	Surface Mount	0.154 in	3.9 mm	14-SOIC	-55 °C	125 °C	4.5 V	5.5 V	1.9 V	2.1 V	33 ns	4 mA	4 mA	2	Schmitt Trigger	0.5 V	0.6 V	NAND Gate
Texas Instruments CD74HCT132MT	4	Surface Mount	0.154 in	3.9 mm	14-SOIC	-55 °C	125 °C	4.5 V	5.5 V	1.9 V	2.1 V	33 ns	4 mA	4 mA	2	Schmitt Trigger	0.5 V	0.6 V	NAND Gate
Texas Instruments CD74HCT132E	4	Through Hole	0.3 "	7.62 mm	14-DIP	-55 °C	125 °C	4.5 V	5.5 V	1.9 V	2.1 V	33 ns	4 mA	4 mA	2	Schmitt Trigger	0.5 V	0.6 V	NAND Gate

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 0.66
		10	$ 0.58
		25	$ 0.54
		100	$ 0.44
		250	$ 0.41
		500	$ 0.35
		1000	$ 0.28
		2500	$ 0.25
		5000	$ 0.24
Texas Instruments	TUBE	1	$ 0.55
		100	$ 0.37
		250	$ 0.29
		1000	$ 0.19

Description

General part information

CD74HCT132 Series

This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y =A ● Bin positive logic.

Documents

Technical documentation and resources

CD54HCT132, CD74HCT132 High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger datasheet

Data sheet

CD74HCT132E

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CD74HCT132E

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Technical Specifications

CD74HCT132 Series

Pricing

Description

CD74HCT132 Series

Documents

CD54HCT132, CD74HCT132 High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger datasheet

CMOS Power Consumption and CPD Calculation (Rev. B)

SN54/74HCT CMOS Logic Family Applications and Restrictions

Implications of Slow or Floating CMOS Inputs (Rev. E)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

LOGIC Pocket Data Book (Rev. B)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Designing With Logic (Rev. C)

Signal Switch Data Book (Rev. A)

Logic Guide (Rev. AB)

TI IBIS File Creation, Validation, and Distribution Processes

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

CD74HCT132 Series