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Technical Specifications
Parameters and characteristics for this part
| Specification | CD4011BPWR |
|---|---|
| Current - Output High, Low [custom] | 3.4 mA |
| Current - Output High, Low [custom] | 3.4 mA |
| Current - Quiescent (Max) [Max] | 1 çA |
| Input Logic Level - High [Max] | 11 V |
| Input Logic Level - High [Min] | 3.5 V |
| Input Logic Level - Low [Max] | 4 V |
| Input Logic Level - Low [Min] | 1.5 V |
| Logic Type | NAND Gate |
| Max Propagation Delay @ V, Max CL | 90 ns |
| Mounting Type | Surface Mount |
| Number of Circuits | 4 |
| Number of Inputs | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 14-TSSOP |
| Package / Case [custom] | 0.173 " |
| Package / Case [custom] | 4.4 mm |
| Supplier Device Package | 14-TSSOP |
| Voltage - Supply [Max] | 18 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.46 | |
| 10 | $ 0.39 | |||
| 25 | $ 0.36 | |||
| 100 | $ 0.29 | |||
| 250 | $ 0.27 | |||
| 500 | $ 0.23 | |||
| 1000 | $ 0.18 | |||
| Digi-Reel® | 1 | $ 0.46 | ||
| 10 | $ 0.39 | |||
| 25 | $ 0.36 | |||
| 100 | $ 0.29 | |||
| 250 | $ 0.27 | |||
| 500 | $ 0.23 | |||
| 1000 | $ 0.18 | |||
| Tape & Reel (TR) | 2000 | $ 0.16 | ||
| 6000 | $ 0.15 | |||
| 10000 | $ 0.14 | |||
| 50000 | $ 0.13 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.28 | |
| 100 | $ 0.19 | |||
| 250 | $ 0.15 | |||
| 1000 | $ 0.10 | |||
Description
General part information
CD4011UB Series
CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.
The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PWR suffix). The CD4011B and CD4023B types also are supplied in 14-lead thin shrink small-outline packages (PW suffix).
CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.
Documents
Technical documentation and resources
