Integrated Circuits (ICs)

CD4011BME4

Unknown

Texas Instruments

IC GATE NAND 4CH 2-INP 14SOIC

Deep-Dive with AI

Search across all available documentation for this part.

DocumentsLogic Guide

Integrated Circuits (ICs)

CD4011BME4

Unknown

Texas Instruments

IC GATE NAND 4CH 2-INP 14SOIC

Deep-Dive with AI

DocumentsLogic Guide

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	CD4011BME4

Current - Output High, Low [custom]	3.4 mA
Current - Output High, Low [custom]	3.4 mA
Current - Quiescent (Max) [Max]	1 çA
Input Logic Level - High [Max]	11 V
Input Logic Level - High [Min]	3.5 V
Input Logic Level - Low [Max]	4 V
Input Logic Level - Low [Min]	1.5 V
Logic Type	NAND Gate
Max Propagation Delay @ V, Max CL	90 ns
Mounting Type	Surface Mount
Number of Circuits	4
Number of Inputs	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Package / Case	14-SOIC
Package / Case [x]	0.154 in
Package / Case [y]	3.9 mm
Voltage - Supply [Max]	18 V
Voltage - Supply [Min]	3 V

CD4011UB Series

4-ch, 2-input, 3-V to 18-V NAND gates

Part	Operating Temperature [Min]	Operating Temperature [Max]	Logic Type	Input Logic Level - High [Max]	Input Logic Level - High [Min]	Number of Inputs	Package / Case [x]	Package / Case	Package / Case [y]	Mounting Type	Number of Circuits	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Input Logic Level - Low [Max]	Input Logic Level - Low [Min]	Current - Quiescent (Max) [Max]	Voltage - Supply [Max]	Voltage - Supply [Min]	Supplier Device Package	Package / Case [custom]	Package / Case [custom]	Max Propagation Delay @ V, Max CL
Texas Instruments CD4011UBNSR	-55 °C	125 °C	NAND Gate	12.5 V	4 V	2	0.209 "	14-SOIC	5.3 mm	Surface Mount	4	3.4 mA	3.4 mA	2.5 V	1 V	1 çA	18 V	3 V	14-SO
Texas Instruments CD4011BPWE4	-55 °C	125 °C	NAND Gate	11 V	3.5 V	2		14-TSSOP		Surface Mount	4	3.4 mA	3.4 mA	4 V	1.5 V	1 çA	18 V	3 V	14-TSSOP	0.173 "	4.4 mm	90 ns
Texas Instruments CD4011UBM96	-55 °C	125 °C	NAND Gate	12.5 V	4 V	2	0.154 in	14-SOIC	3.9 mm	Surface Mount	4	3.4 mA	3.4 mA	2.5 V	1 V	1 çA	18 V	3 V
Texas Instruments CD4011UBPW	-55 °C	125 °C	NAND Gate	12.5 V	4 V	2		14-TSSOP		Surface Mount	4	3.4 mA	3.4 mA	2.5 V	1 V	1 çA	18 V	3 V	14-TSSOP	0.173 "	4.4 mm
Texas Instruments CD4011BM	-55 °C	125 °C	NAND Gate	11 V	3.5 V	2	0.154 in	14-SOIC	3.9 mm	Surface Mount	4	3.4 mA	3.4 mA	4 V	1.5 V	1 çA	18 V	3 V				90 ns
Texas Instruments CD4011BME4	-55 °C	125 °C	NAND Gate	11 V	3.5 V	2	0.154 in	14-SOIC	3.9 mm	Surface Mount	4	3.4 mA	3.4 mA	4 V	1.5 V	1 çA	18 V	3 V				90 ns
Texas Instruments CD4011UBMT	-55 °C	125 °C	NAND Gate	12.5 V	4 V	2	0.154 in	14-SOIC	3.9 mm	Surface Mount	4	3.4 mA	3.4 mA	2.5 V	1 V	1 çA	18 V	3 V
Texas Instruments CD4011BPWRG4	-55 °C	125 °C	NAND Gate	11 V	3.5 V	2		14-TSSOP		Surface Mount	4	3.4 mA	3.4 mA	4 V	1.5 V	1 çA	18 V	3 V	14-TSSOP	0.173 "	4.4 mm	90 ns
Texas Instruments CD4011UBEG4	-55 °C	125 °C	NAND Gate	12.5 V	4 V	2	0.3 "	14-DIP	7.62 mm	Through Hole	4	3.4 mA	3.4 mA	2.5 V	1 V	1 çA	18 V	3 V
Texas Instruments CD4011BPWR	-55 °C	125 °C	NAND Gate	11 V	3.5 V	2		14-TSSOP		Surface Mount	4	3.4 mA	3.4 mA	4 V	1.5 V	1 çA	18 V	3 V	14-TSSOP	0.173 "	4.4 mm	90 ns

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 1.79
		10	$ 1.14
		25	$ 0.97
		100	$ 0.77
		250	$ 0.68
		500	$ 0.62
		1000	$ 0.57

Description

General part information

CD4011UB Series

CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PWR suffix). The CD4011B and CD4023B types also are supplied in 14-lead thin shrink small-outline packages (PW suffix).

Documents

Technical documentation and resources

Logic Guide

Datasheet