Specification	CD74HC107M96

Clock Frequency	60 MHz
Current - Output High, Low [custom]	5.2 mA
Current - Output High, Low [custom]	5.2 mA
Current - Quiescent (Iq)	4 çA
Function	Reset
Input Capacitance	10 pF
Max Propagation Delay @ V, Max CL	29 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Output Type	Complementary
Package / Case	14-SOIC
Package / Case [x]	0.154 in
Package / Case [y]	3.9 mm
Trigger Type	Negative Edge
Type	JK Type
Voltage - Supply [Max]	6 V
Voltage - Supply [Min]	2 V

CD74HC107 Series

High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset

Part	Number of Elements	Current - Quiescent (Iq)	Output Type	Trigger Type	Number of Bits per Element	Operating Temperature [Max]	Operating Temperature [Min]	Function	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Clock Frequency	Input Capacitance	Package / Case [x]	Package / Case [y]	Package / Case	Mounting Type	Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Max Propagation Delay @ V, Max CL
Texas Instruments CD74HC107MTE4	2	4 çA	Complementary	Negative Edge	1	125 °C	-55 °C	Reset	5.2 mA	5.2 mA	60 MHz	10 pF	0.154 in	3.9 mm	14-SOIC	Surface Mount	JK Type	2 V	6 V	29 ns
Texas Instruments CD74HC107EG4	2	4 çA	Complementary	Negative Edge	1	125 °C	-55 °C	Reset	5.2 mA	5.2 mA	60 MHz	10 pF	0.3 "	7.62 mm	14-DIP	Through Hole	JK Type	2 V	6 V	29 ns
Texas Instruments CD74HC107M96	2	4 çA	Complementary	Negative Edge	1	125 °C	-55 °C	Reset	5.2 mA	5.2 mA	60 MHz	10 pF	0.154 in	3.9 mm	14-SOIC	Surface Mount	JK Type	2 V	6 V	29 ns
Texas Instruments CD74HC107MT	2	4 çA	Complementary	Negative Edge	1	125 °C	-55 °C	Reset	5.2 mA	5.2 mA	60 MHz	10 pF	0.154 in	3.9 mm	14-SOIC	Surface Mount	JK Type	2 V	6 V	29 ns
Texas Instruments CD74HC107MG4	2	4 çA	Complementary	Negative Edge	1	125 °C	-55 °C	Reset	5.2 mA	5.2 mA	60 MHz	10 pF	0.154 in	3.9 mm	14-SOIC	Surface Mount	JK Type	2 V	6 V	29 ns
Texas Instruments CD74HC107E	2	4 çA	Complementary	Negative Edge	1	125 °C	-55 °C	Reset	5.2 mA	5.2 mA	60 MHz	10 pF	0.3 "	7.62 mm	14-DIP	Through Hole	JK Type	2 V	6 V	29 ns

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.82
		10	$ 0.72
		25	$ 0.68
		100	$ 0.55
		250	$ 0.52
		500	$ 0.44
		1000	$ 0.35
	Digi-Reel®	1	$ 0.82
		10	$ 0.72
		25	$ 0.68
		100	$ 0.55
		250	$ 0.52
		500	$ 0.44
		1000	$ 0.35
	Tape & Reel (TR)	2500	$ 0.13
		5000	$ 0.15
		7500	$ 0.15
		12500	$ 0.15
		17500	$ 0.14
		25000	$ 0.14
		62500	$ 0.14
Texas Instruments	LARGE T&R	1	$ 0.30
		100	$ 0.21
		250	$ 0.16
		1000	$ 0.11

Description

General part information

CD74HC107 Series

The ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.

These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.

This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.

Documents

Technical documentation and resources

CD74HC107M96

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CD74HC107M96

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Technical Specifications

CD74HC107 Series

Pricing

Description

CD74HC107 Series

Documents

CMOS Power Consumption and CPD Calculation (Rev. B)

Logic Guide (Rev. AB)

Input and Output Characteristics of Digital Integrated Circuits

Signal Switch Data Book (Rev. A)

Power-Up Behavior of Clocked Devices (Rev. B)

Live Insertion

LOGIC Pocket Data Book (Rev. B)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Designing With Logic (Rev. C)

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

CD54HC107, CD74HC107, CD54HCT107, CD74HCT107 datasheet (Rev. D)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

TI IBIS File Creation, Validation, and Distribution Processes

SN54/74HCT CMOS Logic Family Applications and Restrictions

CD74HC107 Series