Specification	SN74LVCZ240APWR

Current - Output High, Low	24 mA
Logic Type	Inverting, Buffer
Mounting Type	Surface Mount
Number of Bits per Element	4
Number of Elements	2
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	3-State
Package / Case	20-TSSOP
Package / Case [x]	0.173 in
Package / Case [y]	4.4 mm
Supplier Device Package	20-TSSOP
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	2.7 V

SN74LVCZ240A Series

8-ch, 2.7-V to 3.6-V inverters with 3-state outputs

Part	Logic Type	Number of Bits per Element	Package / Case [y]	Package / Case	Package / Case [x]	Number of Elements	Output Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Mounting Type	Current - Output High, Low	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case	Package / Case [y]
Texas Instruments SN74LVCZ240APWR	Buffer Inverting	4	4.4 mm	20-TSSOP	0.173 in	2	3-State	2.7 V	3.6 V	20-TSSOP	Surface Mount	24 mA	85 °C	-40 °C
Texas Instruments SN74LVCZ240AN	Buffer Inverting	4		20-DIP		2	3-State	2.7 V	3.6 V	20-PDIP	Through Hole	24 mA	85 °C	-40 °C	7.62 mm	0.3 in
Texas Instruments SN74LVCZ240ANSR	Buffer Inverting	4		20-SOIC		2	3-State	2.7 V	3.6 V	20-SO	Surface Mount	24 mA	85 °C	-40 °C	5.3 mm	0.209 "
Texas Instruments SN74LVCZ240ADW	Buffer Inverting	4	0.295 in	20-SOIC		2	3-State	2.7 V	3.6 V	20-SOIC	Surface Mount	24 mA	85 °C	-40 °C			7.5 mm
Texas Instruments SN74LVCZ240APWRG4	Buffer Inverting	4	4.4 mm	20-TSSOP	0.173 in	2	3-State	2.7 V	3.6 V	20-TSSOP	Surface Mount	24 mA	85 °C	-40 °C
Texas Instruments SN74LVCZ240ADGVR	Buffer Inverting	4	0.173 in	20-TFSOP		2	3-State	2.7 V	3.6 V	20-TVSOP	Surface Mount	24 mA	85 °C	-40 °C			4.4 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 1.33
		10	$ 1.19
		25	$ 1.13
		100	$ 0.93
		250	$ 0.87
		500	$ 0.77
		1000	$ 0.60
	Digi-Reel®	1	$ 1.33
		10	$ 1.19
		25	$ 1.13
		100	$ 0.93
		250	$ 0.87
		500	$ 0.77
		1000	$ 0.60
	Tape & Reel (TR)	2000	$ 0.56
		6000	$ 0.54
		10000	$ 0.52
Texas Instruments	LARGE T&R	1	$ 0.99
		100	$ 0.76
		250	$ 0.56
		1000	$ 0.40

Description

General part information

SN74LVCZ240A Series

This octal buffer/driver is designed for 2.7-V to 3.6-V VCCoperation.

The SN74LVCZ240A is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

This device is organized as two 4-bit buffers/drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

Documents

Technical documentation and resources

SN74LVCZ240APWR

Deep-Dive with AI

SN74LVCZ240APWR

Deep-Dive with AI

Technical Specifications

SN74LVCZ240A Series

Pricing

Description

SN74LVCZ240A Series

Documents

Datasheet

How to Select Little Logic (Rev. A)

Input and Output Characteristics of Digital Integrated Circuits

Logic Guide (Rev. AB)

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

Live Insertion

Signal Switch Data Book (Rev. A)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

LVC Characterization Information

Texas Instruments Little Logic Application Report

Design Summary for WCSP Little Logic (Rev. B)

Low-Voltage Logic (LVC) Designer's Guide

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

LOGIC Pocket Data Book (Rev. B)

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

Understanding Advanced Bus-Interface Products Design Guide

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

CMOS Power Consumption and CPD Calculation (Rev. B)

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Standard Linear & Logic for PCs, Servers & Motherboards

Selecting the Right Level Translation Solution (Rev. A)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Little Logic Guide 2018 (Rev. G)

TI IBIS File Creation, Validation, and Distribution Processes

SN74LVCZ240A Series