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SNJ54S85J
Integrated Circuits (ICs)

CD4516BF

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Texas Instruments

CMOS PRESETTABLE BINARY UP/DOWN COUNTER

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SNJ54S85J
Integrated Circuits (ICs)

CD4516BF

Active
Texas Instruments

CMOS PRESETTABLE BINARY UP/DOWN COUNTER

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics for this part

SpecificationCD4516BF
Count Rate11 MHz
DirectionUp, Down
Logic TypeBinary Counter
Mounting TypeThrough Hole
Number of Bits per Element4
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case7.62 mm, 0.3 in
Package / Case16-CDIP
ResetAsynchronous
Supplier Device Package16-CDIP
TimingSynchronous
Trigger TypePositive Edge
Voltage - Supply [Max]18 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
Texas InstrumentsTUBE 1$ 17.55
100$ 15.32
250$ 11.82
1000$ 10.57

Description

General part information

CD4516B-MIL Series

CD4510B Presettable BCD Up/Down Counter and the CD4516 Presettable Binary Up/Down Counter consist of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. These counters can be cleared by a high level on the RESET line, and can be preset to any binary number present on the jam inputs by a high level on the PRESET ENABLE line. The CD4510B will count out of non-BCD counter states in a maximum of two clock pulses in the up mode, and a maximum of four clock pulses in the down mode.

If the CARRY-IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY-OUT of a less significant stage to the CARRY-IN of a more significant stage.

The CD4510B and CD4516B can be cascaded in the ripple mode by connecting the CARRY-OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY-OUT must be gated with the clock, and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the subsequent counting stage. (See Fig.15).

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