
AD5372BSTZ
Active32-CHANNEL, 16-BIT, SERIAL INPUT, VOLTAGE-OUTPUT DAC
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AD5372BSTZ
Active32-CHANNEL, 16-BIT, SERIAL INPUT, VOLTAGE-OUTPUT DAC
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Technical Specifications
Parameters and characteristics for this part
| Specification | AD5372BSTZ |
|---|---|
| Architecture | String DAC |
| Data Interface | DSP, SPI |
| Differential Output | False |
| INL/DNL (LSB) | ±4 (Max), ±1 (Max) |
| Mounting Type | Surface Mount |
| Number of Bits | 16 |
| Number of D/A Converters | 32 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Voltage - Buffered |
| Package / Case | 64-LQFP |
| Reference Type | External |
| Settling Time | 30 µs |
| Supplier Device Package | 64-LQFP (10x10) |
| Voltage - Supply, Analog [Max] | 16.5 V |
| Voltage - Supply, Analog [Min] | -4.5 V, 9 V |
| Voltage - Supply, Digital [Max] | 5.5 V |
| Voltage - Supply, Digital [Min] | 2.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 114.71 | |
| 10 | $ 93.01 | |||
| 25 | $ 87.48 | |||
| 80 | $ 87.44 | |||
Description
General part information
AD5372 Series
The AD5372 /AD5373contain 32, 16-bit or 14-bit digital-to-analog converters (DACs) in a single 64-lead LQFP. The devices provide buffered voltage outputs with a nominal span of 4× the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility, the device is divided into four groups of eight DACs. Two offset DACs allow the output range of the groups to be altered. Group 0 can be adjusted by Offset DAC 0, and Group 1 to Group 3 can be adjusted by Offset DAC 1.The AD5372 / AD5373 offer guaranteed operation over a wide supply range: VSSfrom −16.5 V to −4.5 V and VDDfrom 9 V to 16.5 V. The output amplifier headroom requirement is 1.4 V operating with a load current of 1 mA.The AD5372 / AD5373 have a high-speed serial interface, which is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds of up to 50 MHz.The DAC registers are updated on reception of new data. All the outputs can be updated simultaneously by taking theLDACinput low. Each channel has a programmable gain and an offset adjust register.Each DAC output is gained and buffered on-chip with respect to an external SIGGNDx input. The DAC outputs can also be switched to SIGGNDx via theCLRpin.APPLICATIONSLevel setting in automatic test equipment (ATE)Variable optical attenuators (VOA)Optical switchesIndustrial control systemsInstrumentation