SN74AUP1G126YFPR
ActiveBUFFER/LINE DRIVER 1-CH NON-INVERTING 3-ST CMOS 6-PIN DSBGA T/R
Deep-Dive with AI
Search across all available documentation for this part.
SN74AUP1G126YFPR
ActiveBUFFER/LINE DRIVER 1-CH NON-INVERTING 3-ST CMOS 6-PIN DSBGA T/R
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AUP1G126YFPR |
|---|---|
| Current - Output High, Low [custom] | 4 mA |
| Current - Output High, Low [custom] | 4 mA |
| Logic Type | Buffer, Non-Inverting |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | 3-State |
| Package / Case | 6-XFBGA, DSBGA |
| Supplier Device Package | 6-DSBGA |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 0.8 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.57 | |
| 10 | $ 0.50 | |||
| 25 | $ 0.47 | |||
| 100 | $ 0.39 | |||
| 250 | $ 0.36 | |||
| 500 | $ 0.31 | |||
| 1000 | $ 0.24 | |||
| Digi-Reel® | 1 | $ 0.57 | ||
| 10 | $ 0.50 | |||
| 25 | $ 0.47 | |||
| 100 | $ 0.39 | |||
| 250 | $ 0.36 | |||
| 500 | $ 0.31 | |||
| 1000 | $ 0.24 | |||
| Tape & Reel (TR) | 3000 | $ 0.22 | ||
| 6000 | $ 0.21 | |||
| 15000 | $ 0.20 | |||
| 30000 | $ 0.19 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.43 | |
| 100 | $ 0.29 | |||
| 250 | $ 0.23 | |||
| 1000 | $ 0.15 | |||
Description
General part information
SN74AUP1G126 Series
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (seeAUP – The Lowest-Power FamilyandExcellent Signal Integrity).
This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low. This device has the input-disable feature, which allows floating input signals.
To assure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Documents
Technical documentation and resources
