Integrated Circuits (ICs)

AM5K2E04XABDA4

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SITARA PROCESSOR: QUAD-ARM CORTEX-A15

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Search across all available documentation for this part.

DocumentsARM CorePac User Guide for KeyStone II Devices Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A)+52

Integrated Circuits (ICs)

AM5K2E04XABDA4

Active

Texas Instruments

SITARA PROCESSOR: QUAD-ARM CORTEX-A15

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DocumentsARM CorePac User Guide for KeyStone II Devices Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A)+52

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	AM5K2E04XABDA4

Additional Interfaces	SPI, UART, EBI/EMI, PCIe, TSIP, I2C, USIM
Co-Processors/DSP	Network
Core Processor	ARM® Cortex®-A15
Ethernet	1GbE (8), 10GbE (2)
Graphics Acceleration	False
Mounting Type	Surface Mount
Number of Cores/Bus Width [custom]	4 Core
Number of Cores/Bus Width [custom]	32 Bit
Operating Temperature [Max]	100 °C
Operating Temperature [Min]	-40 °C
Package / Case	1089-BFBGA, FCBGA
RAM Controllers	DDR3, SRAM
Speed	1.4 GHz
Supplier Device Package	1089-FCBGA (27x27)
USB	USB 3.0 (2)
Voltage - I/O	1.5 V, 1.35 V, 3.3 V, 1.8 V

AM5K2E04 Series

Sitara processor: quad-Arm Cortex-A15

Part	Supplier Device Package	Mounting Type	Speed	Voltage - I/O	Core Processor	Additional Interfaces	Number of Cores/Bus Width [custom]	Number of Cores/Bus Width [custom]	RAM Controllers	Co-Processors/DSP	USB	Package / Case	Ethernet	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments AM5K2E04XABD4	1089-FCBGA (27x27)	Surface Mount	1.4 GHz	1.35 V 1.5 V 1.8 V 3.3 V	ARM® Cortex®-A15	EBI/EMI I2C PCIe SPI TSIP UART USIM	4 Core	32 Bit	DDR3 SRAM	Network	USB 3.0 (2)	1089-BFBGA FCBGA	10GbE (2) 1GbE (8)	85 °C	0 °C
Texas Instruments AM5K2E04XABDA4	1089-FCBGA (27x27)	Surface Mount	1.4 GHz	1.35 V 1.5 V 1.8 V 3.3 V	ARM® Cortex®-A15	EBI/EMI I2C PCIe SPI TSIP UART USIM	4 Core	32 Bit	DDR3 SRAM	Network	USB 3.0 (2)	1089-BFBGA FCBGA	10GbE (2) 1GbE (8)	100 °C	-40 °C
Texas Instruments AM5K2E04XABD25	1089-FCBGA (27x27)	Surface Mount	1.25 GHz	1.35 V 1.5 V 1.8 V 3.3 V	ARM® Cortex®-A15	EBI/EMI I2C PCIe SPI TSIP UART USIM	4 Core	32 Bit	DDR3 SRAM	Network	USB 3.0 (2)	1089-BFBGA FCBGA	10GbE (2) 1GbE (8)	85 °C	0 °C

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tray	40	$ 182.46
Texas Instruments	JEDEC TRAY (5+1)	1	$ 180.65
		100	$ 175.22
		250	$ 145.88
		1000	$ 135.83

Description

General part information

AM5K2E04 Series

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

Documents

Technical documentation and resources

AM5K2E04XABDA4

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AM5K2E04XABDA4

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Technical Specifications

AM5K2E04 Series

Pricing

Description

AM5K2E04 Series

Documents

ARM CorePac User Guide for KeyStone II Devices

Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A)

C66x DSP Cache User's Guide

General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide

AM5K2E04/02 Multicore ARM KeyStone II System-on-Chip (SoC) datasheet (Rev. D)

Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C)

PCIe Use Cases for KeyStone Devices

Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H)

Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide

Hardware Design Guide for KeyStone II Devices

Differentiating AM5K2E02 and AM5K2E04 SoCs from Alternate ARM® Cortex®-A15 Devic

Video Infrastructure - Applications of the K2E, K2H platforms

Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide

Throughput Performance Guide for KeyStone II Devices (Rev. B)

External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A)

DDR3 Design Requirements for KeyStone Devices (Rev. D)

Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices

Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide

Save power and costs with TI's K2E on-chip networking features

Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B)

KeyStone™-II-based processors: 10G Ethernet as an optical interface

AM5K2E04/02 KeyStone SoC Silicon Errata (Silicon Rev 1.0) (Rev. B)

64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A)

DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C)

PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D)

Optimizing Loops on the C66x DSP

Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A)

KeyStone II DDR3 interface bring-up

ARM Bootloader User Guide for KeyStone II Devices

ARM Assembly Language Tools v5.2 User's Guide (Rev. M)

Clocking Spreadsheet for K2E Device Family

Thermal Design Guide for DSP and Arm Application Processors (Rev. B)

Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A)

Debug and Trace for KeyStone II Devices User's Guide

Keystone Multicore Device Family Schematic Checklist

Industrial Imaging: Applications of the K2H and K2E platforms

Power Management of KS2 Device (Rev. C)

Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A)

How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS

Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide

ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J)

HyperLink for KeyStone Devices User's Guide (Rev. C)

Multicore Programming Guide (Rev. B)

Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG

Clocking Design Guide for KeyStone Devices

KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A)

10 Gigabit Ethernet Switch Subsystem User Guide for KeyStone II Devices

Using Arm ROM Bootloader on Keystone II Devices

Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide

Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A)

Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I)

Keystone II DDR3 Initialization

Power Consumption Summary for K2E System-on-Chip (SoC) Device Family

Keystone II DDR3 Debug Guide

AM5K2E04 Series