Specification	SN74ALVCH16373DGGR

Circuit [custom]	8
Circuit [custom]	8
Current - Output High, Low	24 mA
Delay Time - Propagation	1 ns
Independent Circuits	2
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State
Package / Case	48-TFSOP
Package / Case	0.24 in
Package / Case [custom]	6.1 mm
Supplier Device Package	48-TSSOP
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	1.65 V

SN74ALVCH16373 Series

16-Bit Transparent D-Type Latch With 3-State Outputs

Part	Logic Type	Circuit [custom]	Circuit [custom]	Package / Case [y]	Package / Case	Package / Case [y]	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply [Min]	Voltage - Supply [Max]	Current - Output High, Low	Independent Circuits	Output Type	Mounting Type	Supplier Device Package	Delay Time - Propagation	Supplier Device Package [x]	Supplier Device Package [y]	Package / Case	Package / Case [custom]
Texas Instruments SN74ALVCH16373DLR	D-Type Transparent Latch	8	8	0.295 in	48-BSSOP	7.5 mm	85 °C	-40 °C	1.65 V	3.6 V	24 mA	2	Tri-State	Surface Mount	48-SSOP	1 ns
Texas Instruments 74ALVCH16373GRDR	D-Type Transparent Latch	8	8		54-TFBGA		85 °C	-40 °C	1.65 V	3.6 V	24 mA	2	Tri-State	Surface Mount	54-BGA Microstar Junior	1 ns	8	5.5
Texas Instruments SN74ALVCH16373KR	D-Type Transparent Latch	8	8		56-VFBGA		85 °C	-40 °C	1.65 V	3.6 V	24 mA	2	Tri-State	Surface Mount	56-BGA Microstar Junior (7x4.5)	1 ns
Texas Instruments 74ALVCH16373ZRDR	D-Type Transparent Latch	8	8		54-TFBGA		85 °C	-40 °C	1.65 V	3.6 V	24 mA	2	Tri-State	Surface Mount	54-BGA Microstar Junior	1 ns	8	5.5
Texas Instruments SN74ALVCH16373DGGR	D-Type Transparent Latch	8	8		48-TFSOP		85 °C	-40 °C	1.65 V	3.6 V	24 mA	2	Tri-State	Surface Mount	48-TSSOP	1 ns			0.24 in	6.1 mm
Texas Instruments SN74ALVCH16373DL	D-Type Transparent Latch	8	8	0.295 in	48-BSSOP	7.5 mm	85 °C	-40 °C	1.65 V	3.6 V	24 mA	2	Tri-State	Surface Mount	48-SSOP	1 ns
Texas Instruments SN74ALVCH16373DGG
Texas Instruments 74ALVCH16373DGGRG4	D-Type Transparent Latch	8	8		48-TFSOP		85 °C	-40 °C	1.65 V	3.6 V	24 mA	2	Tri-State	Surface Mount	48-TSSOP	1 ns			0.24 in	6.1 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 2.12
		10	$ 1.90
		25	$ 1.80
		100	$ 1.53
		250	$ 1.44
		500	$ 1.26
		1000	$ 1.04
	Digi-Reel®	1	$ 2.12
		10	$ 1.90
		25	$ 1.80
		100	$ 1.53
		250	$ 1.44
		500	$ 1.26
		1000	$ 1.04
	Tape & Reel (TR)	2000	$ 0.97
		6000	$ 0.93
		10000	$ 0.90
Texas Instruments	LARGE T&R	1	$ 1.59
		100	$ 1.31
		250	$ 0.94
		1000	$ 0.71

Description

General part information

SN74ALVCH16373 Series

This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCCoperation.

The SN74ALVCH16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Documents

Technical documentation and resources

SN74ALVCH16373DGGR

Deep-Dive with AI

SN74ALVCH16373DGGR

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Technical Specifications

SN74ALVCH16373 Series

Pricing

Description

SN74ALVCH16373 Series

Documents

Logic Guide

Understanding Advanced Bus-Interface Products Design Guide

LOGIC Pocket Data Book (Rev. B)

CMOS Power Consumption and CPD Calculation (Rev. B)

Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)

TI IBIS File Creation, Validation, and Distribution Processes

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Input and Output Characteristics of Digital Integrated Circuits

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Live Insertion

Power-Up Behavior of Clocked Devices (Rev. B)

16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS--SN74ALVCH16373 datasheet (Rev. I)

An Overview of Bus-Hold Circuit and the Applications (Rev. B)

ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B)

TI SN74ALVC16835 Component Specification Analysis for PC100

Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Standard Linear & Logic for PCs, Servers & Motherboards

SN74ALVCH16373 Series