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PBGA / 256
Integrated Circuits (ICs)

VSC8582XKS-11

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Microchip Technology

2 PORT GBE CU/FIBER PHY WITH IEEE 1588 & MACS

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PBGA / 256
Integrated Circuits (ICs)

VSC8582XKS-11

Active
Microchip Technology

2 PORT GBE CU/FIBER PHY WITH IEEE 1588 & MACS

Technical Specifications

Parameters and characteristics for this part

SpecificationVSC8582XKS-11
FunctionEthernet
InterfaceGMII, SerDes, TBI, SPI
Mounting TypeSurface Mount
Number of Circuits1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Package / Case256-BGA
Supplier Device Package256-PBGA
Supplier Device Package [x]17
Supplier Device Package [y]17

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTray 90$ 42.09
Microchip DirectTRAY 1$ 50.50
25$ 42.09
100$ 38.26
1000$ 35.35
5000$ 33.53

Description

General part information

VSC8582 Series

The dual port VSC8582 GbE PHY with Intellisec and VeriTime is ideal for securing cloud network applications including e-commerce, databases, collaboration, smart grid, video, and enterprise or government communications.

Intellisec enables a realistic and affordable Layer 2 MACsec security solution. Intellisec is a patent-pending technology enabling IEEE 802.1AE MACsec encryption end-to-end over any network, including multi-operator and cloud-based networks, independent of the network's awareness of security protocols. Intellisec is not limited to traditional MACsec link-based box-to-box applications. Likewise, Intellisec scales easily with the number of interfaces delivering significant cost savings in network deployment.

VeriTime™ is Microchip's patent-pending timing technology that delivers the industry's most accurate IEEE 1588v2 timing implementation. Integration of MACsec with IEEE 1588v2 time stamping in the PHY is an efficient and low cost method to protect data passing through the network while maintaining highly accurate time of day (ToD). For these applications, the device supports daisy-chaining of SPI interfaces for IEEE 1588v2 time stamping to reduce the number of pins required on a target ASIC, SoC or FPGA.