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TSSOP (PW)
Integrated Circuits (ICs)

CD4023BPW

Obsolete
Texas Instruments

THREE-CHANNEL 3-INPUT 3V-TO-18V NAND GATE

TSSOP (PW)
Integrated Circuits (ICs)

CD4023BPW

Obsolete
Texas Instruments

THREE-CHANNEL 3-INPUT 3V-TO-18V NAND GATE

Technical Specifications

Parameters and characteristics for this part

SpecificationCD4023BPW
Current - Output High, Low [custom]3.4 mA
Current - Output High, Low [custom]3.4 mA
Current - Quiescent (Max) [Max]1 çA
Input Logic Level - High [Max]11 V
Input Logic Level - High [Min]3.5 V
Input Logic Level - Low [Max]4 V
Input Logic Level - Low [Min]1.5 V
Logic TypeNAND Gate
Max Propagation Delay @ V, Max CL90 ns
Mounting TypeSurface Mount
Number of Circuits3
Number of Inputs3
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case14-TSSOP
Package / Case [custom]0.173 "
Package / Case [custom]4.4 mm
Supplier Device Package14-TSSOP
Voltage - Supply [Max]18 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 1.98
10$ 1.26
25$ 1.07
100$ 0.86
250$ 0.76
500$ 0.69
1000$ 0.64
Texas InstrumentsTUBE 1$ 0.97
100$ 0.75
250$ 0.55
1000$ 0.39

Description

General part information

CD4023B Series

CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PWR suffix). The CD4011B and CD4023B types also are supplied in 14-lead thin shrink small-outline packages (PW suffix).

CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.