
AT25SF321-SHD-B
Obsolete32MBIT, 2.5V MINIMUM SPI SERIAL FLASH MEMORY WITH DUAL-I/O AND QUAD-I/O SUPPORT
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AT25SF321-SHD-B
Obsolete32MBIT, 2.5V MINIMUM SPI SERIAL FLASH MEMORY WITH DUAL-I/O AND QUAD-I/O SUPPORT
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Technical Specifications
Parameters and characteristics for this part
| Specification | AT25SF321-SHD-B |
|---|---|
| Clock Frequency | 104 MHz |
| Memory Format | FLASH |
| Memory Interface | SPI - Quad I/O |
| Memory Organization | 4M x 8 |
| Memory Size | 32 Gbit |
| Memory Type | Non-Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 8-SOIC |
| Package / Case [x] | 0.209 " |
| Package / Case [y] | 5.3 mm |
| Supplier Device Package | 8-SOIC |
| Technology | FLASH - NOR |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 2.5 V |
| Write Cycle Time - Word, Page [custom] | 5 ms |
| Write Cycle Time - Word, Page [custom] | 5 µs |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
AT25SF321B Series
The AT25SF321 serial interface Flash memory device is designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25SF321 is ideal for data storage as well, eliminating the need for additional data storage devices.
The erase block sizes of the AT25SF321 have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that occurs with large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density.
The device also contains three pages of Security Register that can be used for purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. These Security Register pages can be individually locked.
Documents
Technical documentation and resources