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16-DIP SOT38-1
Integrated Circuits (ICs)

SN74S112AN

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Texas Instruments

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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16-DIP SOT38-1
Integrated Circuits (ICs)

SN74S112AN

Active
Texas Instruments

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74S112AN
Clock Frequency125 MHz
Current - Output High, Low [custom]1 mA
Current - Output High, Low [custom]20 mA
Current - Quiescent (Iq)252 mA
FunctionReset, Set(Preset)
Max Propagation Delay @ V, Max CL7 ns
Mounting TypeThrough Hole
Number of Bits per Element1
Number of Elements2
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Output TypeComplementary
Package / Case0.3 in
Package / Case16-DIP
Package / Case7.62 mm
Supplier Device Package16-PDIP
Trigger TypeNegative Edge
TypeJK Type
Voltage - Supply [Max]5.25 V
Voltage - Supply [Min]4.75 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 2.89
10$ 1.89
25$ 1.63
100$ 1.33
250$ 1.19
500$ 1.10
1000$ 1.03
2500$ 1.02
Texas InstrumentsTUBE 1$ 2.12
100$ 1.75
250$ 1.25
1000$ 0.94

Description

General part information

SN74S112A Series

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The SN54LS112A and SN54S112 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS112A and SN74S112A are characterized for operation from 0°C to 70°C.

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.