
AD9641BCPZ-80
Active14-BIT, 80 MSPS/155 MSPS, 1.8 V SERIAL OUTPUT ANALOG-TO-DIGITAL CONVERTER (ADC)
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AD9641BCPZ-80
Active14-BIT, 80 MSPS/155 MSPS, 1.8 V SERIAL OUTPUT ANALOG-TO-DIGITAL CONVERTER (ADC)
Technical Specifications
Parameters and characteristics for this part
| Specification | AD9641BCPZ-80 |
|---|---|
| Architecture | Pipelined |
| Configuration | S/H-ADC |
| Data Interface | JESD204A |
| Input Type | Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 1 |
| Number of Bits | 14 |
| Number of Inputs | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 32-WFQFN Exposed Pad, CSP |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | Internal |
| Sampling Rate (Per Second) | 80 M |
| Supplier Device Package | 32-LFCSP (5x5) |
| Voltage - Supply, Analog [Max] | 1.9 V |
| Voltage - Supply, Analog [Min] | 1.7 V |
| Voltage - Supply, Digital [Max] | 1.9 V |
| Voltage - Supply, Digital [Min] | 1.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 13 | $ 45.55 | |
Description
General part information
AD9641 Series
The AD9641 is a 14-bit, 80 MSPS/155 MSPS analog-to-digital converter (ADC) with a high speed serial output interface. The AD9641 is designed to support communications applications where high performance, combined with low cost, small size, and versatility, is desired. The JESD204A high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth, differential sample-and-hold, analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases the design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.The ADC output data is routed directly to the JESD204A serial output port. This output is at CML voltage levels. A CMOS or LVDS synchronization input (DSYNC) is provided.The flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.The AD9641 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.APPLICATIONSCommunicationsDiversity radio systemsMultimode digital receivers (3G and 4G)GSM, EDGE, W-CDMA, LTE,CDMA2000, WiMAX, TD-SCDMASmart antenna systemsGeneral-purpose software radiosBroadband data applicationsUltrasound equipmentPRODUCT HIGHLIGHTSAn on-chip PLL allows users to provide a single ADC sampling clock. The PLL multiplies the ADC sampling clock to produce the corresponding JESD204A data rate clock.The configurable JESD204A output block coded data rate supports up to 1.6 Gbps.A proprietary differential input maintains excellent SNR performance for input frequencies up to 250 MHz.Operation is from a single 1.8 V power supply.The standard serial port interface (SPI) supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), controlling the clock DCS, power-down, test modes, voltage reference mode, and serial output configuration.
Documents
Technical documentation and resources