Specification	SN74ALVCH16269DGGR

Current - Output High, Low	24 mA
Logic Type	Registered Bus Exchanger
Mounting Type	Surface Mount
Number of Circuits [Max]	24 Bit
Number of Circuits [Min]	12
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Package / Case	6.1 mm
Package / Case	0.24 in
Package / Case	56-TFSOP
Supplier Device Package	56-TSSOP
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	1.65 V

SN74ALVCH16269 Series

12-bit to 24-bit registered bus exchanger with 3-state outputs

Part	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply [Min]	Voltage - Supply [Max]	Current - Output High, Low	Logic Type	Number of Circuits [Min]	Number of Circuits [Max]	Supplier Device Package	Package / Case	Package / Case	Package / Case	Mounting Type
Texas Instruments SN74ALVCH16269DL	85 °C	-40 °C	1.65 V	3.6 V	24 mA	Registered Bus Exchanger	12	24 Bit	56-SSOP	0.295 in	56-BSSOP	7.5 mm	Surface Mount
Texas Instruments SN74ALVCH16269DLR	85 °C	-40 °C	1.65 V	3.6 V	24 mA	Registered Bus Exchanger	12	24 Bit	56-SSOP	0.295 in	56-BSSOP	7.5 mm	Surface Mount
Texas Instruments SN74ALVCH16269DGGR	85 °C	-40 °C	1.65 V	3.6 V	24 mA	Registered Bus Exchanger	12	24 Bit	56-TSSOP	0.24 in	56-TFSOP	6.1 mm	Surface Mount

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 2.20
	Digi-Reel®	1	$ 2.20
	Tape & Reel (TR)	2000	$ 1.01
		6000	$ 0.97
		10000	$ 0.93
Texas Instruments	LARGE T&R	1	$ 1.66
		100	$ 1.37
		250	$ 0.98
		1000	$ 0.74

Description

General part information

SN74ALVCH16269 Series

This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCCoperation.

The SN74ALVCH16269 is used in applications in which two separate ports must be multiplexed onto, or demultiplexed from, a single port. The device is particularly suitable as an interface between synchronous DRAMs and high-speed microprocessors.

Data is stored in the internal B-port registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKENA)\ inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port. For data transfer in the B-to-A direction, a single storage register is provided. The select (SEL)\ line selects 1B or 2B data for the A outputs. The register on the A output permits the fastest possible data transfer, extending the period during which the data is valid on the bus. The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by the active-low output enables (OEA\, OEB1\, OEB2)\.