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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ALVCH16269DLR |
|---|---|
| Current - Output High, Low | 24 mA |
| Logic Type | Registered Bus Exchanger |
| Mounting Type | Surface Mount |
| Number of Circuits [Max] | 24 Bit |
| Number of Circuits [Min] | 12 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 0.295 in |
| Package / Case | 56-BSSOP |
| Package / Case | 7.5 mm |
| Supplier Device Package | 56-SSOP |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
SN74ALVCH16269 Series
This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16269 is used in applications in which two separate ports must be multiplexed onto, or demultiplexed from, a single port. The device is particularly suitable as an interface between synchronous DRAMs and high-speed microprocessors.
Data is stored in the internal B-port registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKENA)\ inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port. For data transfer in the B-to-A direction, a single storage register is provided. The select (SEL)\ line selects 1B or 2B data for the A outputs. The register on the A output permits the fastest possible data transfer, extending the period during which the data is valid on the bus. The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by the active-low output enables (OEA\, OEB1\, OEB2)\.
Documents
Technical documentation and resources
