
ADS54J42IRMPT
ActiveDUAL-CHANNEL, 14-BIT, 625-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC)
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ADS54J42IRMPT
ActiveDUAL-CHANNEL, 14-BIT, 625-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC)
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Technical Specifications
Parameters and characteristics for this part
| Specification | ADS54J42IRMPT |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 72-VFQFN Exposed Pad |
| Supplier Device Package | 72-VQFN (10x10) |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 250 | $ 435.00 | |
| Texas Instruments | SMALL T&R | 1 | $ 403.68 | |
| 100 | $ 365.40 | |||
| 250 | $ 354.96 | |||
| 1000 | $ 348.00 | |||
Description
General part information
ADS54J42 Series
The ADS54J42 is a low-power, wide-bandwidth, 14-bit, 625-MSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –157 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 6.25 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J42 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.
The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.
The ADS54J42 is a low-power, wide-bandwidth, 14-bit, 625-MSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –157 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 6.25 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J42 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.
Documents
Technical documentation and resources