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64-QFN
Integrated Circuits (ICs)

ADS6445MRGCTEP

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Texas Instruments

QUAD-CHANNEL, 14-BIT, 125-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC) - ENHANCED-PRODUCT

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64-QFN
Integrated Circuits (ICs)

ADS6445MRGCTEP

Active
Texas Instruments

QUAD-CHANNEL, 14-BIT, 125-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC) - ENHANCED-PRODUCT

Technical Specifications

Parameters and characteristics for this part

SpecificationADS6445MRGCTEP
ArchitecturePipelined
ConfigurationS/H-ADC
Data InterfaceLVDS - Serial
FeaturesSimultaneous Sampling
Input TypeDifferential
Mounting TypeSurface Mount
Number of A/D Converters4
Number of Bits14
Number of Inputs4
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case64-VFQFN Exposed Pad
Ratio - S/H:ADC1:1
Reference TypeExternal, Internal
Sampling Rate (Per Second)125 M
Supplier Device Package64-VQFN (9x9)
Voltage - Supply, Analog [Max]3.6 V
Voltage - Supply, Analog [Min]3 V
Voltage - Supply, Digital [Max]3.6 V
Voltage - Supply, Digital [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 230.32
10$ 220.59
25$ 215.72
Digi-Reel® 1$ 230.32
10$ 220.59
25$ 215.72
Tape & Reel (TR) 250$ 207.61
Texas InstrumentsSMALL T&R 1$ 186.29
100$ 168.62
250$ 163.80
1000$ 160.59

Description

General part information

ADS6445-EP Series

The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of high performance 14-bit 125/105/80/65 MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.

The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.

An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.