
MC100EP451FAR2G
Active3.3 V / 5.0 V ECL 6-BIT DIFFERENTIAL REGISTER WITH MASTER RESET
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MC100EP451FAR2G
Active3.3 V / 5.0 V ECL 6-BIT DIFFERENTIAL REGISTER WITH MASTER RESET
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Technical Specifications
Parameters and characteristics for this part
| Specification | MC100EP451FAR2G |
|---|---|
| Clock Frequency | 3 GHz |
| Current - Quiescent (Iq) | 135 mA |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 6 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Complementary |
| Package / Case | 32-LQFP |
| Supplier Device Package | 32-LQFP (7x7) |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | -5.5 V |
| Voltage - Supply [Min] | -3 V |
Pricing
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Description
General part information
MC100EP451 Series
The MC10/100EP451 is a 6-bit fully differential register with common clock and single ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75k-ohm pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < VEE+ 1.2 V, the clamp will override and force the output to a default state. When in the default state, and since the flip-flop is edge triggered, the output reaches a determined, but not predicted, valid state.The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW.The 100 Series contains temperature compensation.
Documents
Technical documentation and resources