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16-SOT-23-THIN
Integrated Circuits (ICs)

SN74HCS594DYYR

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Texas Instruments

EIGHT-BIT SHIFT REGISTERS WITH SCHMITT-TRIGGER INPUTS AND WITH OUTPUT REGISTERS

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16-SOT-23-THIN
Integrated Circuits (ICs)

SN74HCS594DYYR

Active
Texas Instruments

EIGHT-BIT SHIFT REGISTERS WITH SCHMITT-TRIGGER INPUTS AND WITH OUTPUT REGISTERS

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74HCS594DYYR
FunctionSerial to Parallel
Logic TypeShift Register
Mounting TypeSurface Mount
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output TypePush-Pull
Supplier Device Package16-SOT-23-THIN
Voltage - Supply [Max]6 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 0.45
10$ 0.39
25$ 0.36
100$ 0.29
250$ 0.27
500$ 0.23
1000$ 0.18
Digi-Reel® 1$ 0.45
10$ 0.39
25$ 0.36
100$ 0.29
250$ 0.27
500$ 0.23
1000$ 0.18
Tape & Reel (TR) 3000$ 0.15
6000$ 0.14
9000$ 0.14
15000$ 0.13
21000$ 0.13
Texas InstrumentsLARGE T&R 1$ 0.13
100$ 0.08
250$ 0.06
1000$ 0.04

Description

General part information

SN74HCS594-Q1 Series

The SN74HCS594-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel outputs. Separate clocks and direct overriding clear ( SRCLR, RCLR) inputs are provided for both the shift and storage register. A serial output (Q H’) is provided for cascading.

Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register is one count pulse ahead of the storage register.

The SN74HCS594-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel outputs. Separate clocks and direct overriding clear ( SRCLR, RCLR) inputs are provided for both the shift and storage register. A serial output (Q H’) is provided for cascading.

Documents

Technical documentation and resources