Deep-Dive with AI
Search across all available documentation for this part.
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | DS90LV110TMTC |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Frequency - Max [Max] | 400 MHz |
| Input | LVPECL, LVDS, PECL |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVDS |
| Package / Case | 28-TSSOP |
| Package / Case | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Ratio - Input:Output [custom] | 1:10 |
| Supplier Device Package | 28-TSSOP |
| Type | Fanout Buffer (Distribution) |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 144 | $ 8.31 | |
Description
General part information
DS90LV110AT Series
DS90LV110A is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 200MHz.
The DS90LV110A accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks.
The LVDS outputs can be put into TRI-STATE by use of the enable pin.
Documents
Technical documentation and resources
No documents available
