
SN74LS191N
ActiveSYNCHRONOUS 4-BIT UP/DOWN COUNTERS WITH UP/DOWN MODE CONTROL
Deep-Dive with AI
Search across all available documentation for this part.

SN74LS191N
ActiveSYNCHRONOUS 4-BIT UP/DOWN COUNTERS WITH UP/DOWN MODE CONTROL
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74LS191N |
|---|---|
| Count Rate | 25 MHz |
| Direction | Up, Down |
| Logic Type | Binary Counter |
| Mounting Type | Through Hole |
| Number of Bits per Element | 4 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Package / Case | 0.3 in |
| Package / Case | 16-DIP |
| Package / Case | 7.62 mm |
| Supplier Device Package | 16-PDIP |
| Timing | Synchronous |
| Trigger Type | Positive Edge |
| Voltage - Supply [Max] | 5.25 V |
| Voltage - Supply [Min] | 4.75 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 1.38 | |
| 10 | $ 1.24 | |||
| 25 | $ 1.17 | |||
| 100 | $ 0.96 | |||
| 250 | $ 0.90 | |||
| 500 | $ 0.80 | |||
| 1000 | $ 0.63 | |||
| 2500 | $ 0.59 | |||
| 5000 | $ 0.56 | |||
| Texas Instruments | TUBE | 1 | $ 1.13 | |
| 100 | $ 0.87 | |||
| 250 | $ 0.64 | |||
| 1000 | $ 0.46 | |||
Description
General part information
SN74LS191 Series
The '190, 'LS190, '191, and 'LS191 are synchronous, reversible up/down counters having a complexity of 58 equivalent gates. The '191 and 'LS191 are 4-bit binary counters and the '190 and 'LS190 are BCD counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters.
The outputs of the four master-slave flip-flops are triggered on a low-to-high transition of the clock input if the enable input is low. A high at the enable input inhibits counting. Level changes at the enable input should be made only when the clock input is high. The direction of the count is determined by the level of the down/up input. When low, the counter count up and when high, it counts down. A false clock may occur if the down/up input changes while the clock is low. A false ripple carry may occur if both the clock and enable are low and the down/up input is high during a load pulse.
These counters are fully programmable; that is, the outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.
Documents
Technical documentation and resources