Zenode.ai Logo
Beta
16 SOIC
Integrated Circuits (ICs)

SN74LS191DE4

Obsolete
Texas Instruments

IC BINARY COUNTER 4-BIT 16SOIC

Deep-Dive with AI

Search across all available documentation for this part.

16 SOIC
Integrated Circuits (ICs)

SN74LS191DE4

Obsolete
Texas Instruments

IC BINARY COUNTER 4-BIT 16SOIC

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LS191DE4
Count Rate25 MHz
DirectionUp, Down
Logic TypeBinary Counter
Mounting TypeSurface Mount
Number of Bits per Element4
Number of Elements1
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Package / Case16-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
Supplier Device Package16-SOIC
TimingSynchronous
Trigger TypePositive Edge
Voltage - Supply [Max]5.25 V
Voltage - Supply [Min]4.75 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$

Description

General part information

SN74LS191 Series

The '190, 'LS190, '191, and 'LS191 are synchronous, reversible up/down counters having a complexity of 58 equivalent gates. The '191 and 'LS191 are 4-bit binary counters and the '190 and 'LS190 are BCD counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters.

The outputs of the four master-slave flip-flops are triggered on a low-to-high transition of the clock input if the enable input is low. A high at the enable input inhibits counting. Level changes at the enable input should be made only when the clock input is high. The direction of the count is determined by the level of the down/up input. When low, the counter count up and when high, it counts down. A false clock may occur if the down/up input changes while the clock is low. A false ripple carry may occur if both the clock and enable are low and the down/up input is high during a load pulse.

These counters are fully programmable; that is, the outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.

Documents

Technical documentation and resources

No documents available