DAC3482IZAY
ActiveDUAL-CHANNEL, 16-BIT, 1.25-GSPS, 1X-16X INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC)
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DAC3482IZAY
ActiveDUAL-CHANNEL, 16-BIT, 1.25-GSPS, 1X-16X INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC)
Technical Specifications
Parameters and characteristics for this part
| Specification | DAC3482IZAY |
|---|---|
| Architecture | Current Source |
| Data Interface | LVDS - Parallel |
| Differential Output | True |
| INL/DNL (LSB) | 4 LSB, 2 LSB |
| Mounting Type | Surface Mount |
| Number of Bits | 16 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Current - Unbuffered |
| Package / Case | 196-LFBGA |
| Reference Type | External, Internal |
| Settling Time | 10 ns |
| Voltage - Supply, Analog [Max] | 3.46 V |
| Voltage - Supply, Analog [Min] | 3.14 V |
| Voltage - Supply, Digital [Max] | 1.32 V |
| Voltage - Supply, Digital [Min] | 1.14 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 160 | $ 44.32 | |
| Texas Instruments | JEDEC TRAY (5+1) | 1 | $ 48.30 | |
| 100 | $ 42.94 | |||
| 250 | $ 35.30 | |||
| 1000 | $ 31.57 | |||
Description
General part information
DAC3482 Series
The DAC3482 is a very low power, high dynamic range, dual-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25GSPS.
The device includes features that simplify the design of complex transmit architectures: 2x to 16x digital interpolation filters with over 90dB of stop-band attenuation simplify the data interface and reconstruction filters. A complex mixer allows flexible carrier placement. A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications.
Digital data is input to the device through a flexible LVDS data bus with on-chip termination. Data can be input either word-wide or byte-wide. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices.
Documents
Technical documentation and resources
