Specification	LMK04228NKDR

Differential - Input:Output [custom]	True
Differential - Input:Output [custom]	True
Divider/Multiplier	Yes/No
Frequency - Max [Max]	3.08 GHz
Input	LVDS, LVCMOS, LVPECL
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output	LVDS, LVPECL, LVCMOS
Package / Case	64-WFQFN Exposed Pad
PLL	True
Ratio - Input:Output	3:15
Supplier Device Package	64-WQFN (9x9)
Type	Jitter Cleaner
Voltage - Supply [Max]	3.45 V
Voltage - Supply [Min]	3.15 V

LMK04228 Series

Ultra low-noise clock jitter cleaner with dual loop PLLs

Part	Differential - Input:Output [custom]	Differential - Input:Output [custom]	PLL	Ratio - Input:Output	Frequency - Max [Max]	Type	Mounting Type	Package / Case	Operating Temperature [Max]	Operating Temperature [Min]	Input	Number of Circuits	Voltage - Supply [Max]	Voltage - Supply [Min]	Supplier Device Package	Output	Divider/Multiplier
Texas Instruments LMK04228NKDT				3:15	3.08 GHz	Jitter Cleaner	Surface Mount	64-WFQFN Exposed Pad	85 °C	-40 °C	LVCMOS LVDS LVPECL	1	3.45 V	3.15 V	64-WQFN (9x9)	LVCMOS LVDS LVPECL	Yes/No
Texas Instruments LMK04228NKDR				3:15	3.08 GHz	Jitter Cleaner	Surface Mount	64-WFQFN Exposed Pad	85 °C	-40 °C	LVCMOS LVDS LVPECL	1	3.45 V	3.15 V	64-WQFN (9x9)	LVCMOS LVDS LVPECL	Yes/No

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 11.11
	Digi-Reel®	1	$ 11.11
	Tape & Reel (TR)	2000	$ 6.07
Texas Instruments	LARGE T&R	1	$ 7.67
		100	$ 6.70
		250	$ 5.17
		1000	$ 4.62

Description

General part information

LMK04228 Series

The LMK04228 device is the industry’s high performance clock conditioner with JEDEC JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high performance outputs for traditional clocking systems.

The high performance combined with features like the ability to trade off between power or performance, dual VCOs, holdover, and per-output adjustable analog and digital delay make the LMK04228 ideal for providing flexible high performance clocking trees.

Documents

Technical documentation and resources

LMK04228 Ultra-Low Noise, JESD204B-Compliant Clock Jitter Cleaner With Dual-Loop PLLs datasheet (Rev. A)

Data sheet