LMK04228 Series

Ultra low-noise clock jitter cleaner with dual loop PLLs

Catalog

Ultra low-noise clock jitter cleaner with dual loop PLLs

Part	Differential - Input:Output [custom]	Differential - Input:Output [custom]	PLL	Ratio - Input:Output	Frequency - Max [Max]	Type	Mounting Type	Package / Case	Operating Temperature [Max]	Operating Temperature [Min]	Input	Number of Circuits	Voltage - Supply [Max]	Voltage - Supply [Min]	Supplier Device Package	Output	Divider/Multiplier
Texas Instruments LMK04228NKDT				3:15	3.08 GHz	Jitter Cleaner	Surface Mount	64-WFQFN Exposed Pad	85 °C	-40 °C	LVCMOS LVDS LVPECL	1	3.45 V	3.15 V	64-WQFN (9x9)	LVCMOS LVDS LVPECL	Yes/No
Texas Instruments LMK04228NKDR				3:15	3.08 GHz	Jitter Cleaner	Surface Mount	64-WFQFN Exposed Pad	85 °C	-40 °C	LVCMOS LVDS LVPECL	1	3.45 V	3.15 V	64-WQFN (9x9)	LVCMOS LVDS LVPECL	Yes/No

Catalog

Ultra low-noise clock jitter cleaner with dual loop PLLs

Key Features

• JEDEC JESD204B SupportUltra-Low RMS Jitter156 fs RMS Jitter (12 kHz to 20 MHz)245 fs RMS Jitter (100 Hz to 20 MHz)–162.5 dBc/Hz Noise Floor at 245.76 MHzUp to 14 Differential Device Clocks from PLL2Up to 7 SYSREF ClocksMaximum Clock Output Frequency: 1.25 GHzLVPECL, LVDS Programmable Outputs From PLL2Buffered VCXO or Crystal Output From PLL1LVPECL, LVDS, 2xLVCMOS ProgrammableDual Loop PLLatinum™ PLL ArchitecturePLL1Up to 3 Redundant Input ClocksAutomatic and Manual Switch-Over ModesHitless Switching and LOSIntegrated Low-Noise Crystal Oscillator CircuitHoldover Mode When Input Clocks are LostPLL2Normalized [1 Hz] PLL Noise Floor of–224 dBc/HzPhase Detector Rate up to 155 MHzOSCin Frequency-DoublerTwo Integrated Low-Noise VCOs50% Duty Cycle Output Divides, 1 to 32(Even and Odd)Precision Digital Delay25-ps Step Analog DelayMulti-Mode: Dual PLL or Single PLLIndustrial Temperature Range: –40°C to 85°C3.15-V to 3.45-V OperationPackage: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)JEDEC JESD204B SupportUltra-Low RMS Jitter156 fs RMS Jitter (12 kHz to 20 MHz)245 fs RMS Jitter (100 Hz to 20 MHz)–162.5 dBc/Hz Noise Floor at 245.76 MHzUp to 14 Differential Device Clocks from PLL2Up to 7 SYSREF ClocksMaximum Clock Output Frequency: 1.25 GHzLVPECL, LVDS Programmable Outputs From PLL2Buffered VCXO or Crystal Output From PLL1LVPECL, LVDS, 2xLVCMOS ProgrammableDual Loop PLLatinum™ PLL ArchitecturePLL1Up to 3 Redundant Input ClocksAutomatic and Manual Switch-Over ModesHitless Switching and LOSIntegrated Low-Noise Crystal Oscillator CircuitHoldover Mode When Input Clocks are LostPLL2Normalized [1 Hz] PLL Noise Floor of–224 dBc/HzPhase Detector Rate up to 155 MHzOSCin Frequency-DoublerTwo Integrated Low-Noise VCOs50% Duty Cycle Output Divides, 1 to 32(Even and Odd)Precision Digital Delay25-ps Step Analog DelayMulti-Mode: Dual PLL or Single PLLIndustrial Temperature Range: –40°C to 85°C3.15-V to 3.45-V OperationPackage: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)

Description

The LMK04228 device is the industry’s high performance clock conditioner with JEDEC JESD204B support. The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high performance outputs for traditional clocking systems. The high performance combined with features like the ability to trade off between power or performance, dual VCOs, holdover, and per-output adjustable analog and digital delay make the LMK04228 ideal for providing flexible high performance clocking trees. The LMK04228 device is the industry’s high performance clock conditioner with JEDEC JESD204B support. The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high performance outputs for traditional clocking systems. The high performance combined with features like the ability to trade off between power or performance, dual VCOs, holdover, and per-output adjustable analog and digital delay make the LMK04228 ideal for providing flexible high performance clocking trees.