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48-NFBGA
Integrated Circuits (ICs)

TS2PCIE2212ZAHRG1

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Texas Instruments

4-CHANNEL PCIE 2:1 MULTIPLEXER/DEMULTIPLEXER PASSIVE FET SWITCH

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48-NFBGA
Integrated Circuits (ICs)

TS2PCIE2212ZAHRG1

Active
Texas Instruments

4-CHANNEL PCIE 2:1 MULTIPLEXER/DEMULTIPLEXER PASSIVE FET SWITCH

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Technical Specifications

Parameters and characteristics for this part

SpecificationTS2PCIE2212ZAHRG1
ApplicationsPCI Express®
Mounting TypeSurface Mount
Multiplexer/Demultiplexer Circuit2:1
Number of Channels [custom]2
On-State Resistance (Max) [Max]17 Ohms
Operating Temperature [Max]85 C
Operating Temperature [Min]0 °C
Package / Case48-TFBGA
Supplier Device Package48-NFBGA (5x5)
Voltage - Supply, Single (V+) [Max]1.9 V
Voltage - Supply, Single (V+) [Min]1.7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 4.66
Digi-Reel® 1$ 4.66
Tape & Reel (TR) 3000$ 2.34
Texas InstrumentsLARGE T&R 1$ 4.47
100$ 3.69
250$ 2.65
1000$ 2.00

Description

General part information

TS2PCIE2212 Series

The TS2PCIE2212 can be used to muxltiplex/demultiplex two PCI Express™ lanes, each representing differential pairs of receive (RX) and transmit (TX) signals. The switch operates at the PCI Express bandwidth standard of 2.5-Gbps signal-processing speed. The device is composed of two banks, with each bank accommodating two sources (source A and source B) and two destinations (destination A and destination B).

When a logic-level low is applied to the control (CTRL) pin, source A is connected to destination A and source B is connected to destination B. When a logic-level high is applied to CTRL, source A is connected to destination B, while source B and destination A are open.

The TS2PCIE2212 can be used to muxltiplex/demultiplex two PCI Express™ lanes, each representing differential pairs of receive (RX) and transmit (TX) signals. The switch operates at the PCI Express bandwidth standard of 2.5-Gbps signal-processing speed. The device is composed of two banks, with each bank accommodating two sources (source A and source B) and two destinations (destination A and destination B).

Documents

Technical documentation and resources