Specification	FDG6321C-F169

Configuration	N and P-Channel
Current - Continuous Drain (Id) @ 25°C	500 mA, 410 mA
Drain to Source Voltage (Vdss)	25 V
FET Feature	Logic Level Gate
Gate Charge (Qg) (Max) @ Vgs	1.5 nC
Gate Charge (Qg) (Max) @ Vgs	2.3 nC
Input Capacitance (Ciss) (Max) @ Vds	62 pF, 50 pF
Mounting Type	Surface Mount
Operating Temperature [Max]	150 °C
Operating Temperature [Min]	-55 °C
Package / Case	6-TSSOP, SC-88, SOT-363
Power - Max [Max]	300 mW
Rds On (Max) @ Id, Vgs	450 mOhm, 1.1 Ohm
Supplier Device Package	SC-70-6
Technology	MOSFET (Metal Oxide)
Vgs(th) (Max) @ Id	1.5 V

FDG6321C Series

Dual N & P Channel Digital FET 25V

Part	Supplier Device Package	Vgs(th) (Max) @ Id	Mounting Type	Gate Charge (Qg) (Max) @ Vgs	Gate Charge (Qg) (Max) @ Vgs	Drain to Source Voltage (Vdss)	Package / Case	Input Capacitance (Ciss) (Max) @ Vds	Power - Max [Max]	Rds On (Max) @ Id, Vgs	Operating Temperature [Min]	Operating Temperature [Max]	Technology	Configuration	Current - Continuous Drain (Id) @ 25°C	FET Feature
ON Semiconductor FDG6321C-F169	SC-70-6	1.5 V	Surface Mount	1.5 nC	2.3 nC	25 V	6-TSSOP SC-88 SOT-363	50 pF 62 pF	300 mW	1.1 Ohm 450 mOhm	-55 °C	150 °C	MOSFET (Metal Oxide)	N and P-Channel	410 mA 500 mA	Logic Level Gate

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

FDG6321C Series

These dual N & P-Channel logic level enhancement mode field effect transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values.