FDG6321C Series

Dual N & P Channel Digital FET 25V

Catalog

Dual N & P Channel Digital FET 25V

Part	Supplier Device Package	Vgs(th) (Max) @ Id	Mounting Type	Gate Charge (Qg) (Max) @ Vgs	Gate Charge (Qg) (Max) @ Vgs	Drain to Source Voltage (Vdss)	Package / Case	Input Capacitance (Ciss) (Max) @ Vds	Power - Max [Max]	Rds On (Max) @ Id, Vgs	Operating Temperature [Min]	Operating Temperature [Max]	Technology	Configuration	Current - Continuous Drain (Id) @ 25°C	FET Feature
ON Semiconductor FDG6321C-F169	SC-70-6	1.5 V	Surface Mount	1.5 nC	2.3 nC	25 V	6-TSSOP SC-88 SOT-363	50 pF 62 pF	300 mW	1.1 Ohm 450 mOhm	-55 °C	150 °C	MOSFET (Metal Oxide)	N and P-Channel	410 mA 500 mA	Logic Level Gate

Catalog

Dual N & P Channel Digital FET 25V

Key Features

• N-Ch0.50 A, 25 VRDS(ON)= 0.45 Ω @ VGS= 4.5 VRDS(ON)= 0.60 Ω @ VGS= 2.7 V

• P-Ch-0.41 A, -25 VRDS(ON)= 1.1 Ω @ VGS= -4.5 VRDS(ON)= 1.5 Ω @ VGS= -2.7 V

• Very small package outline SC70-6.

• Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th)< 1.5 V).

• Gate-Source Zener for ESD ruggedness (>6kV Human Body Model).

Description

These dual N & P-Channel logic level enhancement mode field effect transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values.