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Technical Specifications
Parameters and characteristics for this part
| Specification | SY88943VKG |
|---|---|
| Applications | Optical Networks |
| Mounting Type | Surface Mount |
| Package / Case | 10-MSOP, 10-TFSOP |
| Package / Case [x] | 3 mm |
| Package / Case [x] | 0.118 in |
| Supplier Device Package | 10-MSOP |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 100 | $ 12.17 | |
| Microchip Direct | TUBE | 1 | $ 16.05 | |
| 25 | $ 13.38 | |||
| 100 | $ 12.17 | |||
| 1000 | $ 10.14 | |||
| 5000 | $ 9.35 | |||
| 10000 | $ 8.69 | |||
Description
General part information
SY88943V Series
The SY88943V limiting post amplifier with its high gain and wide bandwidth is ideal for use as a post amplifier in fiber-optic receivers with data rates up to 2.5Gbps. Signals as small as 5mVp-p can be amplified to drive devices with PECL inputs. The SY88943V generates a chatter-free Signal Detect (SD) open collector TTL output.
The SY88943V incorporates a programmable level detect function to identify when the input signal has been lost. This information can be fed back to the EN input of the device to maintain stability under loss of signal condition. Using SDLVL pin, the sensitivity of the level detection can be adjusted. The SDLVL voltage can be set by connecting a resistor divider between VCC and VREF. Figure 3 and Figure 4 show the relationship between input level sensitivity and the voltage set on SDLVL. Figure 5 shows the relationship between input level sensitivity and resistor divider ratio.
The SD output is a TTL open collector output that requires a pull-up resistor for proper operation
Documents
Technical documentation and resources