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Trans MOSFET N/P-CH 25V 0.68A/0.46A 6-Pin SuperSOT T/R
Discrete Semiconductor Products

FDC6321C

Active
ON Semiconductor

MOSFET TRANSISTOR, N AND P CHANNEL, 680 MA, 25 V, 450 MOHM, 4.5 V, 800 MV ROHS COMPLIANT: YES

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Trans MOSFET N/P-CH 25V 0.68A/0.46A 6-Pin SuperSOT T/R
Discrete Semiconductor Products

FDC6321C

Active
ON Semiconductor

MOSFET TRANSISTOR, N AND P CHANNEL, 680 MA, 25 V, 450 MOHM, 4.5 V, 800 MV ROHS COMPLIANT: YES

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationFDC6321C
ConfigurationN and P-Channel
Current - Continuous Drain (Id) @ 25°C680 mA, 460 mA
Drain to Source Voltage (Vdss)25 V
FET FeatureLogic Level Gate
Gate Charge (Qg) (Max) @ Vgs2.3 nC
Input Capacitance (Ciss) (Max) @ Vds50 pF
Mounting TypeSurface Mount
Operating Temperature [Max]150 °C
Operating Temperature [Min]-55 °C
Package / CaseTSOT-23-6, SOT-23-6 Thin
Power - Max [Max]700 mW
Rds On (Max) @ Id, Vgs450 mOhm
Supplier Device PackageSuperSOT™-6
TechnologyMOSFET (Metal Oxide)
Vgs(th) (Max) @ Id1.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 0.61
10$ 0.52
100$ 0.36
500$ 0.28
1000$ 0.23
Digi-Reel® 1$ 0.61
10$ 0.52
100$ 0.36
500$ 0.28
1000$ 0.23
Tape & Reel (TR) 3000$ 0.21
6000$ 0.20
9000$ 0.18
30000$ 0.18
NewarkEach (Supplied on Cut Tape) 1$ 0.82
10$ 0.53
25$ 0.47
50$ 0.41
100$ 0.36
250$ 0.35
500$ 0.28
1000$ 0.25
ON SemiconductorN/A 1$ 0.18

Description

General part information

FDC6321C Series

These dual N & P Channel logic level enhancement mode field effect transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors in load switching applications. Since bias resistors are not required this dual digital FET can replace several digital transistors with different bias resistors.