FDC6321C Series

Dual N & P Channel Digital FET 25V

Catalog

Dual N & P Channel Digital FET 25V

Part	Supplier Device Package	Power - Max [Max]	Input Capacitance (Ciss) (Max) @ Vds	Configuration	Operating Temperature [Min]	Operating Temperature [Max]	Gate Charge (Qg) (Max) @ Vgs	Mounting Type	FET Feature	Technology	Package / Case	Rds On (Max) @ Id, Vgs	Drain to Source Voltage (Vdss)	Current - Continuous Drain (Id) @ 25°C	Vgs(th) (Max) @ Id
ON Semiconductor FDC6321C	SuperSOT™-6	700 mW	50 pF	N and P-Channel	-55 °C	150 °C	2.3 nC	Surface Mount	Logic Level Gate	MOSFET (Metal Oxide)	SOT-23-6 Thin TSOT-23-6	450 mOhm	25 V	460 mA 680 mA	1.5 V

Catalog

Dual N & P Channel Digital FET 25V

Key Features

• N-Ch 25 V, 0.68 A, RDS(ON)= 0.45 Ω @ VGS= 4.5 V

• P-Ch -25 V, -0.46 A, RDS(ON)= 1.1 Ω @ VGS= -4.5 V.

• Very low level gate drive requirements allowing direct operation in 3 V circuits. VGS(th)< 1.0V.

• Gate-Source Zener for ESD ruggedness. >6kV Human Body Model

• Replace multiple dual NPN & PNP digital transistors.

Description

These dual N & P Channel logic level enhancement mode field effect transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors in load switching applications. Since bias resistors are not required this dual digital FET can replace several digital transistors with different bias resistors.