ZL40235LDG1
Active2 X 5 LVPECL/LVDS/HCSL FANOUT BUFFER 40 VQFN 6X6X1MM TRAY ROHS COMPLIANT: YES
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ZL40235LDG1
Active2 X 5 LVPECL/LVDS/HCSL FANOUT BUFFER 40 VQFN 6X6X1MM TRAY ROHS COMPLIANT: YES
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Technical Specifications
Parameters and characteristics for this part
| Specification | ZL40235LDG1 |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Frequency - Max [Max] | 1.6 GHz |
| Input | HCSL, LVDS, LVPECL, SSTL, CML, LVCMOS |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVCMOS, HCSL, LVPECL, LVDS |
| Package / Case | 40-VFQFN Exposed Pad |
| Ratio - Input:Output | 3:5 |
| Supplier Device Package | 40-QFN (6x6) |
| Type | Fanout Buffer (Distribution), Multiplexer |
| Voltage - Supply [Max] | 3.465 V |
| Voltage - Supply [Min] | 1.35 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 5.75 | |
| 25 | $ 4.80 | |||
| 100 | $ 4.63 | |||
| Microchip Direct | TRAY | 1 | $ 5.75 | |
| 25 | $ 4.80 | |||
| 100 | $ 4.36 | |||
| 1000 | $ 4.02 | |||
| 5000 | $ 3.81 | |||
| Newark | Each | 100 | $ 4.36 | |
Description
General part information
ZL40235 Series
The ZL40235 is a programmable or hardware pin controlled low additive jitter, low power 3 x 5 LVPECL/HCSL/LVDS fanout buffer.
Two inputs can accept signal in differential (LVPECL, SSTL, LVDS, HSTL, CML) or single ended (LVPECL or LVCMOS) format and the third input can accept a single ended signal or it can be used to build a crystal oscillator by connecting an external crystal resonator between its XIN and XOUT pins. All the other components for building crystal oscillator are built in device such as load capacitance, series and shunt resistors.
The ZL40235 has five LVPECL/HCSL/LVDS outputs which can be powered from 3.3V or 2.5V supply. Each output can be independently enabled/disabled via SPI bus. The type of each output driver can be programmed to be LVPECL, HCSL or LVDS. Hence, the device can be configured to support application where different signal formats are needed.
