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48-SSOP
Integrated Circuits (ICs)

SN74ACT16373QDLREP

Active
Texas Instruments

ENHANCED PRODUCT 16-CH, 4.5-V TO 5.5-V INVERTERS WITH SCHMITT-TRIGGER INPUTS

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Search across all available documentation for this part.

DocumentsLOGIC Pocket Data Book (Rev. B)Selecting the Right Level Translation Solution (Rev. A)+10
48-SSOP
Integrated Circuits (ICs)

SN74ACT16373QDLREP

Active
Texas Instruments

ENHANCED PRODUCT 16-CH, 4.5-V TO 5.5-V INVERTERS WITH SCHMITT-TRIGGER INPUTS

Deep-Dive with AI

DocumentsLOGIC Pocket Data Book (Rev. B)Selecting the Right Level Translation Solution (Rev. A)+10

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74ACT16373QDLREP
Circuit [custom]8
Circuit [custom]8
Current - Output High, Low [custom]16 mA
Current - Output High, Low [custom]16 mA
Delay Time - Propagation9.3 ns
Independent Circuits2
Logic TypeD-Type Transparent Latch
Mounting TypeSurface Mount
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output TypeTri-State
Package / Case48-BSSOP
Package / Case [y]0.295 in
Package / Case [y]7.5 mm
Supplier Device Package48-SSOP
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 5.83
10$ 5.24
25$ 4.95
100$ 4.29
250$ 4.07
500$ 3.65
Digi-Reel® 1$ 5.83
10$ 5.24
25$ 4.95
100$ 4.29
250$ 4.07
500$ 3.65
Tape & Reel (TR) 1000$ 3.08
2000$ 2.93
Texas InstrumentsLARGE T&R 1$ 4.61
100$ 3.76
250$ 2.95
1000$ 2.50

Description

General part information

SN74ACT16373-EP Series

The SN74ACT16373Q-EP is a 16-bit D-type transparent latch with 3-state outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

This device can be used as two 8-bit latches or one 16-bit latch. The Q outputs of the latches follow the data (D) inputs if the latch-enable (LE) input is taken high. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines in a bus-organized system, without need for interface or pullup components.