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Technical Specifications
Parameters and characteristics for this part
| Specification | TVP7002PZPR |
|---|---|
| Applications | Consumer Video |
| Control Interface | I2C |
| Function | Digitizer |
| Mounting Type | Surface Mount |
| Package / Case | 100-TQFP Exposed Pad |
| Supplier Device Package | 100-HTQFP (14x14) |
| Voltage - Supply [Max] | 2 V, 3.6 V |
| Voltage - Supply [Min] | 1.8 V, 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 8.29 | |
| 10 | $ 7.49 | |||
| 25 | $ 7.14 | |||
| 100 | $ 6.20 | |||
| 250 | $ 5.92 | |||
| 500 | $ 5.40 | |||
| Digi-Reel® | 1 | $ 8.29 | ||
| 10 | $ 7.49 | |||
| 25 | $ 7.14 | |||
| 100 | $ 6.20 | |||
| 250 | $ 5.92 | |||
| 500 | $ 5.40 | |||
| Tape & Reel (TR) | 1000 | $ 4.70 | ||
| 2000 | $ 4.53 | |||
| Texas Instruments | LARGE T&R | 1 | $ 6.35 | |
| 100 | $ 5.17 | |||
| 250 | $ 4.07 | |||
| 1000 | $ 3.45 | |||
Description
General part information
TVP7002 Series
The TVP7002 is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The device supports pixel rates up to 165 MHz. Therefore, it can be used for PC graphics digitizing up to the VESA standard of UXGA (1600 × 1200) resolution at a 60-Hz screen refresh rate, and in video environments for the digitizing of digital TV formats, including HDTV up to 1080p.
The TVP7002 is powered from 3.3-V and 1.9-V supply and integrates a triple high-performance analog-to-digital (A/D) converter with clamping functions and variable gain, independently programmable for each channel. The clamp timing window is provided by an external pulse or can be generated internally. The TVP7002 includes analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction. In addition, TVP7002 can extract discrete HSYNC and VSYNC from composite sync using a sync slicer.
The TVP7002 also contains a complete horizontal phase-locked loop (PLL) block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 12 MHz to 165 MHz.
Documents
Technical documentation and resources
