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Technical Specifications
Parameters and characteristics for this part
| Specification | NB3W1200LMNG |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Divider/Multiplier | False |
| Frequency - Max [Max] | 133 MHz |
| Input | Clock |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output | Clock |
| Package / Case | 64-VFQFN Exposed Pad |
| PLL | Yes with Bypass |
| Ratio - Input:Output | 1:12 |
| Supplier Device Package | 64-QFN (9x9) |
| Voltage - Supply [Max] | 3.465 V |
| Voltage - Supply [Min] | 3.135 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
NB3W1200L Series
The NB3N1200K and NB3W1200L differential clock buffers areDB1200Z and DB1200ZL compliant and are designed to work inconjunction with a PCIe compliant source clock synthesizer to providepoint−to−point clocks to multiple agents. The device is capable ofdistributing the reference clocks for Intel® QuickPath Interconnect(Intel QPI & UPI), PCIe Gen1/Gen2/Gen3/Gen4, SAS, SATA, and Intel ScalableMemory Interconnect (Intel SMI) applications. The VCO of thedevice is optimized to support 100 MHz and 133 MHz frequencyoperation. The NB3N1200K and NB3W1200L utilizepseudo−external feedback topology to achieve low input−to outputdelay variation. The NB3N1200K is configured with the HCSL buffertype, while the NB3W1200L is configured with the low−powerNMOS Push−Pull buffer type.
Documents
Technical documentation and resources