SN74ALVCH373DWR
ActiveOCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
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SN74ALVCH373DWR
ActiveOCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ALVCH373DWR |
|---|---|
| Circuit [custom] | 8 |
| Circuit [custom] | 8 |
| Current - Output High, Low | 24 mA |
| Delay Time - Propagation | 1 ns |
| Independent Circuits | 1 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State |
| Package / Case | 20-SOIC |
| Package / Case [y] | 0.295 in |
| Package / Case [y] | 7.5 mm |
| Supplier Device Package | 20-SOIC |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.83 | |
| 10 | $ 0.74 | |||
| 25 | $ 0.71 | |||
| 100 | $ 0.58 | |||
| 250 | $ 0.54 | |||
| 500 | $ 0.48 | |||
| 1000 | $ 0.38 | |||
| Digi-Reel® | 1 | $ 0.83 | ||
| 10 | $ 0.74 | |||
| 25 | $ 0.71 | |||
| 100 | $ 0.58 | |||
| 250 | $ 0.54 | |||
| 500 | $ 0.48 | |||
| 1000 | $ 0.38 | |||
| Tape & Reel (TR) | 2000 | $ 0.35 | ||
| 6000 | $ 0.34 | |||
| 10000 | $ 0.32 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.62 | |
| 100 | $ 0.47 | |||
| 250 | $ 0.35 | |||
| 1000 | $ 0.25 | |||
Description
General part information
SN74ALVCH373 Series
This octal transparent D-type latch is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
Documents
Technical documentation and resources
