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SOIC (DW)
Integrated Circuits (ICs)

SN74ALVCH373DW

Active
Texas Instruments

OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

Deep-Dive with AI

Search across all available documentation for this part.

DocumentsCMOS Power Consumption and CPD Calculation (Rev. B)Power-Up Behavior of Clocked Devices (Rev. B)+18
SOIC (DW)
Integrated Circuits (ICs)

SN74ALVCH373DW

Active
Texas Instruments

OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

Deep-Dive with AI

DocumentsCMOS Power Consumption and CPD Calculation (Rev. B)Power-Up Behavior of Clocked Devices (Rev. B)+18

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74ALVCH373DW
Circuit [custom]8
Circuit [custom]8
Current - Output High, Low24 mA
Delay Time - Propagation1 ns
Independent Circuits1
Logic TypeD-Type Transparent Latch
Mounting TypeSurface Mount
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeTri-State
Package / Case20-SOIC
Package / Case [y]0.295 in
Package / Case [y]7.5 mm
Supplier Device Package20-SOIC
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]1.65 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 0.66
10$ 0.59
25$ 0.56
100$ 0.46
250$ 0.43
500$ 0.38
1000$ 0.35
Texas InstrumentsTUBE 1$ 0.74
100$ 0.57
250$ 0.42
1000$ 0.30

Description

General part information

SN74ALVCH373 Series

This octal transparent D-type latch is designed for 1.65-V to 3.6-V VCCoperation.

The SN74ALVCH373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.