MC100EP51DG
ActiveFLIP FLOP D-MASTER-SLAVE TYPE POS-EDGE/NEG-EDGE 1-ELEMENT 8-PIN SOIC N TUBE
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MC100EP51DG
ActiveFLIP FLOP D-MASTER-SLAVE TYPE POS-EDGE/NEG-EDGE 1-ELEMENT 8-PIN SOIC N TUBE
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Technical Specifications
Parameters and characteristics for this part
| Specification | MC100EP51DG |
|---|---|
| Clock Frequency | 3 GHz |
| Current - Quiescent (Iq) | 45 mA |
| Function | Reset |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Complementary |
| Package / Case | 8-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Supplier Device Package | 8-SOIC |
| Trigger Type | Negative, Positive |
| Type | D-Type |
| Voltage - Supply [Max] | -5.5 V |
| Voltage - Supply [Min] | -3 V |
Pricing
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Description
General part information
MC100EP51 Series
The MC10/100EP51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices.The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop.The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEEand the CLKbar input will be biased at VCC/ 2.
Documents
Technical documentation and resources
