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54-pin (NJY) package image
Integrated Circuits (ICs)

DS125BR401ANJYT

Active
Texas Instruments

12-GBPS 4-LANE REDRIVER WITH EQUALIZATION

54-pin (NJY) package image
Integrated Circuits (ICs)

DS125BR401ANJYT

Active
Texas Instruments

12-GBPS 4-LANE REDRIVER WITH EQUALIZATION

Technical Specifications

Parameters and characteristics for this part

SpecificationDS125BR401ANJYT
ApplicationsPCIe, SATA, SAS
Capacitance - Input5 pF
Data Rate (Max)12 Gbps
Delay Time80 ps
InputCML
Mounting TypeSurface Mount
Number of Channels4
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
OutputCML
Package / Case54-WFQFN Exposed Pad
Signal ConditioningInput Equalization, Output De-Emphasis
Supplier Device Package54-WQFN (10x5.5)
TypeReDriver, Buffer
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]2.375 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 11.73
10$ 10.78
25$ 10.33
100$ 9.83
Digi-Reel® 1$ 11.73
10$ 10.78
25$ 10.33
100$ 9.83
Tape & Reel (TR) 250$ 9.83
Texas InstrumentsSMALL T&R 1$ 13.06
100$ 11.41
250$ 8.79
1000$ 7.87

Description

General part information

DS125BR401A Series

The DS125BR401A is an extremely low-power high-performance repeater/redriver designed to support four lanes carrying high speed interface up to 12 Gbps. The B-Side receiver’s continuous time linear equalizers (CTLE) provide high frequency boost of up to +24 dB at 6 GHz (12 Gbps) and are capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as backplane traces or twinaxial copper cables. The programmable equalization allows maximum flexibility in the physical placement within the interconnect channel. The A-Side channel has a 10 dB linear equalizer and linear output driver.

The A-Side channel has a settable 3-10 dB linear equalizer coupled to a linear output driver. When operating in SAS-3 and PCIe Gen-3 applications the DS125BR401A preserves transmit signal characteristics allowing the host controller and the end point to negotiate transmit equalizer coefficients. This transparency to the link training protocol aides system level interoperability and minimum latency.

The programmable settings can be applied easily via Terminals, software (SMBus or I2C), or loaded via an external EEPROM. In EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver.