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Crystals, Oscillators, Resonators

LMK61PD0A2-SIAT

Active
Texas Instruments

±50 PPM, ULTRA-LOW JITTER, PIN SELECTABLE, DIFFERENTIAL OSCILLATOR

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QFM (SIA)
Crystals, Oscillators, Resonators

LMK61PD0A2-SIAT

Active
Texas Instruments

±50 PPM, ULTRA-LOW JITTER, PIN SELECTABLE, DIFFERENTIAL OSCILLATOR

Technical Specifications

Parameters and characteristics for this part

SpecificationLMK61PD0A2-SIAT
Base ResonatorCrystal
Frequency - Output 162.5 MHz, 125 MHz, 156.25 MHz, 100 MHz, 212.5 MHz, 312.5 MHz, 106.5 MHz
Height [z]0.045 in
Height [z]1.15 mm
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
OutputLVPECL, HCSL, LVDS
Package / Case8-SMD Module
Size / Dimension [x]7 mm
Size / Dimension [x]0.276 "
Size / Dimension [y]5 mm
Size / Dimension [y]0.197 "
TypeXO (Standard)
Voltage - Supply [Max]3.465 V
Voltage - Supply [Min]3.135 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 13.64
10$ 12.76
50$ 12.32
100$ 11.88
Digi-Reel® 1$ 13.64
10$ 12.76
50$ 12.32
100$ 11.88
Tape & Reel (TR) 250$ 11.88
500$ 11.70
750$ 11.00
Texas InstrumentsSMALL T&R 1$ 14.46
100$ 12.63
250$ 9.74
1000$ 8.71

Description

General part information

LMK61PD0A2 Series

The LMK61PD0A2 is an ultra-low jitter PLLatinum™ pin selectable oscillator that generates commonly used reference clocks. The device is pre-programmed in factory to support seven unique reference clock frequencies that can be selected by pin-strapping each of FS[1:0] to VDD, GND or NC (no connect). Output format is selected between LVPECL, LVDS, or HCSL by pin-strapping OS to VDD, GND or NC. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply.

The LMK61PD0A2 is an ultra-low jitter PLLatinum™ pin selectable oscillator that generates commonly used reference clocks. The device is pre-programmed in factory to support seven unique reference clock frequencies that can be selected by pin-strapping each of FS[1:0] to VDD, GND or NC (no connect). Output format is selected between LVPECL, LVDS, or HCSL by pin-strapping OS to VDD, GND or NC. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply.