LMK61PD0A2 Series

±50 ppm, ultra-low jitter, pin selectable, differential oscillator

Catalog

±50 ppm, ultra-low jitter, pin selectable, differential oscillator

Part	Type	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply [Max]	Voltage - Supply [Min]	Package / Case	Output	Height [z]	Height [z]	Frequency - Output 1	Size / Dimension [x]	Size / Dimension [y]	Size / Dimension [x]	Size / Dimension [y]	Base Resonator
Texas Instruments LMK61PD0A2-SIAT	XO (Standard)	85 °C	-40 °C	3.465 V	3.135 V	8-SMD Module	HCSL LVDS LVPECL	0.045 in	1.15 mm	62.5 MHz 100 MHz 106.5 MHz 125 MHz 156.25 MHz 212.5 MHz 312.5 MHz	7 mm	5 mm	0.276 "	0.197 "	Crystal

Catalog

±50 ppm, ultra-low jitter, pin selectable, differential oscillator

Key Features

• Ultra-low Noise, High PerformanceJitter: 90 fs RMS typical fOUT> 100 MHzPSRR: –70 dBc, robust supply noise immunityFlexible Output Frequency and Format; UserSelectableFrequencies: 62.5 MHz, 100 MHz, 106.25 MHz,125 MHz, 156.25 MHz, 212.5 MHz,312.5 MHzFormats: LVPECL, LVDS or HCSLTotal frequency tolerance of ± 50 ppmInternal memory stores multiple start-upconfigurations, selectable through pin control3.3V operating voltageIndustrial temperature range (–40ºC to +85ºC)7 mm × 5 mm 8-pin packageUltra-low Noise, High PerformanceJitter: 90 fs RMS typical fOUT> 100 MHzPSRR: –70 dBc, robust supply noise immunityFlexible Output Frequency and Format; UserSelectableFrequencies: 62.5 MHz, 100 MHz, 106.25 MHz,125 MHz, 156.25 MHz, 212.5 MHz,312.5 MHzFormats: LVPECL, LVDS or HCSLTotal frequency tolerance of ± 50 ppmInternal memory stores multiple start-upconfigurations, selectable through pin control3.3V operating voltageIndustrial temperature range (–40ºC to +85ºC)7 mm × 5 mm 8-pin package

Description

The LMK61PD0A2 is an ultra-low jitter PLLatinum™ pin selectable oscillator that generates commonly used reference clocks. The device is pre-programmed in factory to support seven unique reference clock frequencies that can be selected by pin-strapping each of FS[1:0] to VDD, GND or NC (no connect). Output format is selected between LVPECL, LVDS, or HCSL by pin-strapping OS to VDD, GND or NC. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply. The LMK61PD0A2 is an ultra-low jitter PLLatinum™ pin selectable oscillator that generates commonly used reference clocks. The device is pre-programmed in factory to support seven unique reference clock frequencies that can be selected by pin-strapping each of FS[1:0] to VDD, GND or NC (no connect). Output format is selected between LVPECL, LVDS, or HCSL by pin-strapping OS to VDD, GND or NC. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply.