LMK5C33216RGCT
ActiveULTRA-LOW JITTER CLOCK SYNCHRONIZER WITH JESD204B FOR WIRELESS COMMUNICATIONS WITH BAW
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LMK5C33216RGCT
ActiveULTRA-LOW JITTER CLOCK SYNCHRONIZER WITH JESD204B FOR WIRELESS COMMUNICATIONS WITH BAW
Technical Specifications
Parameters and characteristics for this part
| Specification | LMK5C33216RGCT |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Divider/Multiplier | Yes/No |
| Frequency - Max [Max] | 3 GHz, 200 MHz, 1 GHz |
| Input | LVDS, LVCMOS, HCSL, LVPECL, Crystal |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVCMOS, CML, LVDS, LVPECL |
| Package / Case | 64-VFQFN Exposed Pad |
| PLL | True |
| Ratio - Input:Output [custom] | 16 |
| Ratio - Input:Output [custom] | 2 |
| Supplier Device Package | 64-VQFN (9x9) |
| Type | Jitter Attenuator, Clock Generator, Clock Synchronizer |
| Voltage - Supply [Max] | 3.465 V |
| Voltage - Supply [Min] | 3.135 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 59.33 | |
| 10 | $ 46.26 | |||
| 25 | $ 42.92 | |||
| 100 | $ 40.00 | |||
| Digi-Reel® | 1 | $ 59.33 | ||
| 10 | $ 46.26 | |||
| 25 | $ 42.92 | |||
| 100 | $ 40.00 | |||
| Tape & Reel (TR) | 250 | $ 43.63 | ||
| Texas Instruments | SMALL T&R | 1 | $ 48.96 | |
| 100 | $ 43.52 | |||
| 250 | $ 35.78 | |||
| 1000 | $ 32.00 | |||
Description
General part information
LMK5C33216 Series
The LMK5C33216 is a high-performance network clock generator, synchronizer, and jitter attenuator with advanced reference clock selection and hitless switching capabilities designed to meet the stringent requirements of communications infrastructure applications.
The LMK5C33216 integrates 3 DPLLs with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a DPLL reference input. The APLL reference determines the long term frequency accuracy.
The 3 APLLs may operate independent of their paired DPLL and be cascaded from another APLL to provide programmable frequency translation. APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) VCBO technology and can generate output clocks with 40-fs RMS jitter independent of the jitter and frequency of the XO and reference inputs. APLL1 and APLL2 provide options for additional frequency domains.
Documents
Technical documentation and resources
