LMK5C33216 Series

Ultra-low jitter clock synchronizer with JESD204B for wireless communications with BAW

Catalog

Ultra-low jitter clock synchronizer with JESD204B for wireless communications with BAW

Part	Frequency - Max [Max]	Input	Number of Circuits	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply [Max]	Voltage - Supply [Min]	Output	Mounting Type	PLL	Package / Case	Differential - Input:Output [custom]	Differential - Input:Output [custom]	Divider/Multiplier	Type	Supplier Device Package	Ratio - Input:Output	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]
Texas Instruments LMK5C33216RGCR	1 GHz 3 GHz 200 MHz	Crystal HCSL LVCMOS LVDS LVPECL	1	85 °C	-40 °C	3.465 V	3.135 V	CML LVCMOS LVDS LVPECL	Surface Mount		64-VFQFN Exposed Pad			Yes/No	Clock Generator Clock Synchronizer Jitter Attenuator	64-VQFN (9x9)	3:16
Texas Instruments LMK5C33216RGCT	1 GHz 3 GHz 200 MHz	Crystal HCSL LVCMOS LVDS LVPECL	1	85 °C	-40 °C	3.465 V	3.135 V	CML LVCMOS LVDS LVPECL	Surface Mount		64-VFQFN Exposed Pad			Yes/No	Clock Generator Clock Synchronizer Jitter Attenuator	64-VQFN (9x9)		16	2

Catalog

Ultra-low jitter clock synchronizer with JESD204B for wireless communications with BAW

Key Features

• BAW APLL with 40 fs RMS jitter at 491.52 MHzThree high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs)Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz-116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20 MHz TDC rateTwo differential or single-ended DPLL inputs1 Hz to 800 MHz differentialHitless switching with phase cancellation and/or phase slew controlPriority based reference selection16 outputs with programmable format1000 MHz LVPECL/LVDS/HSDS3000 MHz CML on OUT4 and OUT6200 MHz LVCMOS on OUT0 and OUT1Single 3.3-V supply with internal LDOsI2C or 3-wire/4-wire SPI interfaceRequires single XO/TCXO/OCXO40-bit DPLL or APLL DCO, < 1 pptHoldover with phase build out upon exitZero delay mode with programmable delayUser programmable EEPROMSupports 105 °C PCB temperatureBAW APLL with 40 fs RMS jitter at 491.52 MHzThree high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs)Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz-116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20 MHz TDC rateTwo differential or single-ended DPLL inputs1 Hz to 800 MHz differentialHitless switching with phase cancellation and/or phase slew controlPriority based reference selection16 outputs with programmable format1000 MHz LVPECL/LVDS/HSDS3000 MHz CML on OUT4 and OUT6200 MHz LVCMOS on OUT0 and OUT1Single 3.3-V supply with internal LDOsI2C or 3-wire/4-wire SPI interfaceRequires single XO/TCXO/OCXO40-bit DPLL or APLL DCO, < 1 pptHoldover with phase build out upon exitZero delay mode with programmable delayUser programmable EEPROMSupports 105 °C PCB temperature

Description

The LMK5C33216 is a high-performance network clock generator, synchronizer, and jitter attenuator with advanced reference clock selection and hitless switching capabilities designed to meet the stringent requirements of communications infrastructure applications. The LMK5C33216 integrates 3 DPLLs with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a DPLL reference input. The APLL reference determines the long term frequency accuracy. The 3 APLLs may operate independent of their paired DPLL and be cascaded from another APLL to provide programmable frequency translation. APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) VCBO technology and can generate output clocks with 40-fs RMS jitter independent of the jitter and frequency of the XO and reference inputs. APLL1 and APLL2 provide options for additional frequency domains. The device is fully programmable through I2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks. The LMK5C33216 is a high-performance network clock generator, synchronizer, and jitter attenuator with advanced reference clock selection and hitless switching capabilities designed to meet the stringent requirements of communications infrastructure applications. The LMK5C33216 integrates 3 DPLLs with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a DPLL reference input. The APLL reference determines the long term frequency accuracy. The 3 APLLs may operate independent of their paired DPLL and be cascaded from another APLL to provide programmable frequency translation. APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) VCBO technology and can generate output clocks with 40-fs RMS jitter independent of the jitter and frequency of the XO and reference inputs. APLL1 and APLL2 provide options for additional frequency domains. The device is fully programmable through I2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks.