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8-MSOP Exp Pad Pkg
Integrated Circuits (ICs)

SN65LVDS9637DGN

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Texas Instruments

IC RECEIVER 0/2 8HVSSOP

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8-MSOP Exp Pad Pkg
Integrated Circuits (ICs)

SN65LVDS9637DGN

Active
Texas Instruments

IC RECEIVER 0/2 8HVSSOP

Technical Specifications

Parameters and characteristics for this part

SpecificationSN65LVDS9637DGN
Data Rate150 Mbps
Mounting TypeSurface Mount
Number of Drivers/Receivers [custom]2
Number of Drivers/Receivers [custom]0
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / CaseExposed Pad, 8-TSSOP, 8-MSOP
Package / Case [custom]0.118 in, 3 mm
ProtocolLVDS
Supplier Device Package8-HVSSOP
TypeReceiver
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 3.27
10$ 2.93
80$ 2.40
320$ 2.28
560$ 2.05
1040$ 1.73
2560$ 1.64
5040$ 1.58
Texas InstrumentsTUBE 1$ 2.73
100$ 2.26
250$ 1.62
1000$ 1.22

Description

General part information

SN65LVDS9637B Series

This family of differential line receivers offers improved performance and features that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS is defined in the TIA/EIA-644 standard. This improved performance represents the second generation of receiver products for this standard, providing a better overall solution for the cabled environment. This generation of products is an extension to TI's overall product portfolio and is not necessarily a replacement for older LVDS receivers.

Improved features include an input common-mode voltage range 2 V wider than the minimum required by the standard. This will allow longer cable lengths by tripling the allowable ground noise tolerance to 3 V between a driver and receiver. TI has additionally introduced an even wider input common-mode voltage range of -4 to 5 V in their SN65LVDS/T33 and SN65LVDS/T34.

Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range.