DAC12DL3200ACF
Active12-BIT, LOW-LATENCY, DUAL 3.2-GSPS OR SINGLE 6.4-GSPS, RF-SAMPLING DAC (LVDS INTERFACE)
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DAC12DL3200ACF
Active12-BIT, LOW-LATENCY, DUAL 3.2-GSPS OR SINGLE 6.4-GSPS, RF-SAMPLING DAC (LVDS INTERFACE)
Technical Specifications
Parameters and characteristics for this part
| Specification | DAC12DL3200ACF |
|---|---|
| Data Interface | LVDS - Parallel |
| Differential Output | False |
| INL/DNL (LSB) | 0.6 LSB, 0.9 LSB |
| Mounting Type | Surface Mount |
| Number of Bits | 12 bits |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Voltage - Unbuffered |
| Package / Case | 256-BBGA, FCBGA |
| Supplier Device Package | 256-FCBGA (17x17) |
| Voltage - Supply, Analog [Max] | 1.05 V, 1.89 V |
| Voltage - Supply, Analog [Min] | -1.71 V, 0.95 V |
| Voltage - Supply, Digital [Max] | 1.05 V, 1.89 V |
| Voltage - Supply, Digital [Min] | -1.71 V, 0.95 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Arrow | N/A | 1 | $ 1917.74 | |
| Digikey | Box | 1 | $ 2750.35 | |
| Texas Instruments | JEDEC TRAY (5+1) | 1 | $ 1924.80 | |
| 100 | $ 1764.40 | |||
| 250 | $ 1668.16 | |||
| 1000 | $ 1604.00 | |||
Description
General part information
DAC12DL3200 Series
The DAC12DL3200 is a very low latency, dual channel, RF sampling digital-to-analog converter (DAC) capable of input and output rates of up to 3.2-GSPS in dual channel mode or 6.4-GSPS in single channel mode. The DAC can transmit signal bandwidths beyond 2 GHz at carrier frequencies approaching 8 GHz when using the multi-Nyquist output modes. The high output frequency range enables direct sampling through C-band (8 GHz) and beyond.
The DAC12DL3200 can be used as an I/Q baseband DAC in dual channel mode. The high sampling rate and output frequency range also makes the DAC12DL3200 capable of arbitrary waveform generation (AWG) and direct digital synthesis (DDS). An integrated DDS block enables single tone and two tone generation on chip.
The DAC12DL3200 has a parallel LVDS interface that consists of up to 48 LVDS pairs and 4 DDR LVDS clocks. A strobe signal is used to synchronize the interface which can be sent over the least significant bit (LSB) or optionally over dedicated strobe LVDS lanes. Each LVDS pair is capable of up to 1.6 Gbps. Multi-device synchronization is supported using a synchronization signal (SYSREF) and is compatible with JESD204B/C clocking devices. SYSREF windowing eases synchronization in multi-device systems.