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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74LS74ADG4 |
|---|---|
| Clock Frequency | 33 MHz |
| Current - Output High, Low [custom] | 400 µA |
| Current - Output High, Low [custom] | 8 mA |
| Current - Quiescent (Iq) | 8 mA |
| Function | Reset, Set(Preset) |
| Max Propagation Delay @ V, Max CL | 40 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output Type | Complementary |
| Package / Case | 14-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.25 V |
| Voltage - Supply [Min] | 4.75 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
SN74LS74A Series
These devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.
The SN54' family is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74' family is characterized for operation from 0°C to 70°C.
These devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.
Documents
Technical documentation and resources
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